1. A battery security device, comprising:
a holder having a containing cavity;
a cover slidably dis-mountable from the holder and having two raised lumps protruding into the containing cavity; and
at least one flexible planar plate disposed between the holder and the cover, being pivotally connected to the holder, and having two elastic arms, each of the elastic arms has a pressed portion and at least one contact portion, wherein the pressed portions project toward the cover, each of the raised lumps of the cover abut against a respective pressed portion, and each contact portion is radially displaced relative to the flexible planar plate into the containing cavity to contact an electrode of a respective battery disposed therein responsive to a force occasioned by a respective raised lump of the cover abutting against the pressed portion of a corresponding elastic arm.
2. The battery security device as claimed in claim 1, wherein the raised lumps and the cover are made integrally in one piece.
3. The battery security device as claimed in claim 1, wherein the raised lumps are rectangular, square, elliptical, round or polygonal.
4. The battery security device as claimed in claim 1, wherein each raised lump includes a push portion, which is capable of applying force on a respective contact portion.
5. The battery security device as claimed in claim 1, wherein the flexible planar plate has two openings punched therethrough, each elastic arm is located in a respective opening and has an end connected to the flexible planar plate.
6. The battery security device as claimed in claim 1, wherein each elastic arm is folded to form the pressed portion.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.
1. A semiconductor integrated circuit, comprising:
a sense amplifier which senses and outputs data read out from memory cells connected to word lines and bit lines, the sense amplifier outputting data in accordance with a potential difference between the potential on the bit line and the potential on a reference bit line; and
a read-out control circuit which has a standby state consuming minimum necessary power and a read state reading out the memory cells, and controls read-out of the memory cells;
wherein the read-out control circuit includes:
a bit line switching circuit which switches whether or not to transmit a potential on the bit line to an input terminal of the sense amplifier;
a first switching control circuit which controls the bit line switching circuit to prevent the potential on the bit line from being transmitted to the input terminal of the sense amplifier during a period of the standby state and a predetermined period after the standby state is released; and
a second switching control circuit which controls the bit line switching circuit to prevent the potential on the reference bit line from being transmitted to the corresponding input terminal of the sense amplifier during the period of the standby state and a predetermined period after the standby state is released.
2. The semiconductor integrated circuit according to claim 1,
wherein the first switching control circuit sets the input terminal of the sense amplifier to a predetermined reference voltage level during the period of the standby state and the predetermined period after the standby state is released.
3. The semiconductor integrated circuit according to claim 1,
wherein the first switching control circuit switches whether or not to transmit the potential on the bit line to the corresponding input terminal of the sense amplifier based on a bit line potential control signal on which a logic inverts at a predetermined period after the standby state elapses; and
the second switching control circuit switches whether or not to transmit the potential on the reference bit line to the corresponding input terminal of the sense amplifier based on the bit line potential control signal.
4. The semiconductor integrated circuit according to claim 1,
wherein the read-out control circuit includes:
a bias transistor which sets the bit line to a predetermined potential at the timing of reading out the memory cells; and
a bias control circuit which controls a gate voltage of the bias transistor;
wherein the first and second switching control circuit decide the predetermined period in conformity to a time when the gate voltage of the bias transistor stabilizes after the standby state is released.
5. The semiconductor integrated circuit according to claim 4,
wherein the first and second switching control circuit decide the predetermined period in conformity to a time when fluctuation of the gate voltage of the bias transistor does not exist any more after the standby state is released.
6. The semiconductor integrated circuit according to claim 1,
wherein the bit line switching circuit has a plurality of transistors which switch whether or not to transmit the potential on the bit line to the input terminal of the sense amplifier and are connected to a plurality of bit lines, respectively; and
the first switching control circuit turns off the plurality of transistors during the period of the standby state and the predetermined period after the standby state is released.
7. The semiconductor integrated circuit according to claim 6,
wherein the first switching control circuit turns on one of the plurality of transistors at the predetermined period after the standby state is released.
8. The semiconductor integrated circuit according to claim 1,
wherein the memory cells are memory cells of a flash memory; and
the first switching control circuit is a decoder which decodes a portion of addresses of the flash memory.
9. A microcomputer, comprising:
a cell array having a plurality of memory cells each connected to word lines and bit lines;
a plurality of sense amplifiers which are provided in units of the plurality of bit lines, sense and output data read out from the plurality of memory cells, each the sense amplifier outputting data in accordance with a potential difference between the potential on the bit line and the potential on a reference bit line; and
a read-out control circuit which has a standby state consuming minimum necessary power and a read state reading out the memory cells, and controls read-out of the memory cells;
wherein the read-out control circuit includes:
a bit line switching circuit which switches whether or not to transmit a potential on the bit line to an input terminal of the corresponding sense amplifier;
a first switching control circuit which controls the bit line switching circuit to prevent the potential on the bit line from being transmitted to the input terminal of the corresponding sense amplifier during a period of the standby state and a predetermined period after the standby state is released; and
a second switching control circuit which controls the bit line switching circuit to prevent the potential on the reference bit line from being transmitted to the input terminal of the corresponding sense amplifier during the period of the standby state and the predetermined period after the standby state is released.
10. The microcomputer according to claim 9,
wherein the first switching control circuit sets the input terminal of the sense amplifier to a predetermined reference voltage level during the period of the standby state and the predetermined period after the standby state is released.
11. The microcomputer according to claim 9,
wherein the first switching control circuit switches whether or not to transmit the potential on the bit line to the corresponding input terminal of the sense amplifier based on a bit line potential control signal on which a logic inverts at a predetermined period after the standby state elapses; and
the second switching control circuit switches whether or not to transmit the potential on the reference bit line to the corresponding input terminal of the sense amplifier based on the bit line potential control signal.
12. The microcomputer according to claim 9,
wherein the read-out control circuit includes:
a bias transistor which sets the bit line to a predetermined potential at the timing of reading out the memory cells; and
a bias control circuit which controls a gate voltage of the bias transistor;
wherein the first and second switching control circuit decide the predetermined period in conformity to a time when the gate voltage of the bias transistor stabilizes after the standby state is released.
13. The microcomputer according to claim 12,
wherein the first and second switching control circuit decide the predetermined period in conformity to a time when fluctuation of the gate voltage of the bias transistor does not exist any more after the standby state is released.
14. The microcomputer according to claim 9,
wherein the bit line switching circuit has a plurality of transistors which switch whether or not to transmit the potential on the bit line to the input terminal of the sense amplifier and are connected to a plurality of bit lines, respectively; and
the first switching control circuit turns off the plurality of transistors during the period of the standby state and the predetermined period after the standby state is released.
15. The microcomputer according to claim 14,
wherein the first switching control circuit turns on one of the plurality of transistors at the predetermined period after the standby state is released.
16. The microcomputer according to claim 9,
wherein the memory cells are memory cells of a flash memory; and
the first switching control circuit is a decoder which decodes a portion of addresses of the flash memory.