1. A light source package comprising:
a first light source configured to emit first light, an imaginary central axis of the first light extending in a first direction;
a second light source configured to emit second light, an imaginary central axis of the second light extending in a second direction that is different from the first direction;
a first optical part including a first concave reflective surface that is configured to reflect at least a first portion of the first light; and
a second optical part configured to spread the second light, the second optical part including a second concave reflective surface that is configured to reflect at least a second portion of the first light.
2. The light source package of claim 1, further comprising:
a reflecting sheet that reflects the first light reflected by the first concave reflective surface of the first optical part; and
a diffusion sheet disposed over the first and second light sources,
wherein the first light reflected by the reflecting sheet is directed toward the diffusion sheet, and
the second light spread by the second optical part is directed toward the diffusion sheet.
3. The light source package of claim 1, wherein the second optical part overlaps the second light source.
4. The light source package of claim 3, wherein
an outer surface of the second optical part includes a groove in a substantially central region of the outer surface, and
the second light source is located below and aligned with the groove.
5. The light source package of claim 4, wherein
a distance from an inner surface to the outer surface of the second optical part above the second light source is shortest.
6. The light source package of claim 1, wherein the first light source and the second light source are electrically connected in series.
7. The light source package of claim 1, wherein the first light source is positioned between the first optical part and the second optical part.
8. The light source package of claim 1, wherein the first concave reflective surface and the second concave reflective surface form one curved surface.
9. The light source package of claim 8, wherein the second concave reflective surface is convex toward the second light source.
10. The light source package of claim 8, wherein the first concave reflective surface extends longer than the second concave reflective surface.
11. The light source package of claim 1 further comprising a heat transfer unit thermally coupled with the first light source and surrounded by the first optical part.
12. The light source package of claim 1, wherein the first optical part is larger than the second optical part in a top view of the light source package.
13. The light source package of claim 1, wherein the first optical part includes at least one of a resin portion and a metal portion.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.
1. A sensor manufacturing method, comprising following steps:
provide a silicon-on-insulator (SOI) substrate, a silicon layer of said SOI substrate is penetrated with at least a trench;
form at least a patterned via through said silicon layer, and form at least a sacrifice layer on said silicon layer, to fill said trench and said patterned via;
remove part of said sacrifice layer, to expose said silicon layer, and form a conduction wiring layer on said sacrifice layer, to connect electrically to said silicon layer, and said conduction wiring layer is provided with at least a hole, with its position corresponding to that of said patterned via; and
through said hole, remove said sacrifice layer in said patterned via.
2. The sensor manufacturing method as claimed in claim 1, wherein in said step of forming said patterned via in said silicon layer, forming said sacrifice layer on said silicon layer, and filling said trench and said patterned via further includes following steps:
utilize thermal oxidation method or plasma enhanced chemical vapor deposition (PECVD) to form an oxidation layer on said silicon layer, to fill said trench;
remove part of said oxidation layer and said silicon layer below, to form said patterned via; and
fill a sacrifice structure in said patterned via, and form said sacrifice layer on said silicon layer.
3. The sensor manufacturing method as claimed in claim 1, wherein in said step of forming said conduction wiring layer on said sacrifice layer, and connecting it electrically to said silicon layer further comprising following steps:
form a first metal layer on said sacrifice layer, to connect it electrically to said silicon layer;
at a position corresponding to said patterned via, form at least an opening in said first metal layer, to expose said sacrifice layer, and form a first insulation layer to fill said opening; and
form a metal wiring layer having said hole on said first metal layer and said first insulation layer, so that said conduction wiring layer is formed on said sacrifice layer.
4. The sensor manufacturing method as claimed in claim 3, wherein in said step of forming said metal wiring layer on said first metal layer and said first insulation layer, form a first insulation block on said first insulation layer, form a second insulation block and a metal block on said first metal layer, such that said first insulation block and said second insulation block are adjacent to said metal block, and are located respectively inside and outside said metal block, to form a second metal layer having said hole on said first insulation block, said second insulation block, and said metal block, and form a second insulation layer in said hole to be located on said first insulation block, so that said metal wiring layer is formed on said first metal layer and said first insulation layer.
5. The sensor manufacturing method as claimed in claim 4, wherein in said step of removing said sacrifice layer in said patterned via through said hole, remove in sequence said second insulation layer, said first insulation block, said first insulation layer, said sacrifice layer inside said first metal layer, said sacrifice layer in said patterned via, and a silicon oxide layer on said SOI substrate, wherein, said first insulation layer, said second insulation layer, said first insulation block, and said second insulation block are made of silicon dioxide.
6. The sensor manufacturing method as claimed in claim 1, wherein deep reactive-ion etching is used to form said patterned via, position of said hole corresponds to that of said trench, and
in said step of removing said sacrifice layer in said patterned via through said hole, remove at the same time said sacrifice layers in said trench and said patterned via; and
in said step of removing said part of said sacrifice layer to expose said silicon layer, remove said part of said sacrifice layer to expose said silicon layer, such that said sacrifice layer has a first sacrifice block and a second sacrifice block, and said second sacrifice block is on an outer perimeter of said first sacrifice block, said first sacrifice layer is made of silicon dioxide, while said second sacrifice block is made of silicon dioxide, silicon carbide, or undoping polysilicon.
7. The sensor manufacturing method as claimed in claim 1, wherein
in said step of removing said sacrifice layer in said patterned via through said hole, use Hydrogen Fluoride (HF) vapor through said hole, or performing wet etching through said hole; and
after said step of removing said sacrifice layer in said patterned via through said hole, a step of forming at least an insulation layer on said conduction wiring layer, to seal off said hole is performed.
8. The sensor manufacturing method as claimed in claim 1, wherein after said step of forming said conduction wiring layer on said sacrifice layer, to connect it electrically to said silicon layer, form an opening in said silicon layer of said SOI substrate, to expose a silicon dioxide layer of said SOI substrate, and position of said opening corresponds to that of said patterned via; and
in said step of removing said sacrifice layer in said patterned via through said hole, remove said sacrifice layer in said patterned via through said hole, so that said opening connects with said patterned via.
9. A sensor manufacturing method, comprising following steps:
provide a silicon substrate, that is provided with at least a trench penetrating through said silicon substrate;
form a sacrifice layer on said silicon substrate, to fill said trench;
remove a part of said sacrifice layer, to expose said silicon substrate, and form a conduction wiring layer on said sacrifice layer, to connect it electrically to said silicon substrate, said conduction wiring layer is provided with at least a hole, and position of said hole corresponds to that of said sacrifice layer on an inner side of said conduction wiring layer;
through said hole, remove said sacrifice layer on said inner side; and
at a position corresponding to said hole, form at least a patterned via penetrating through said silicon substrate.
10. The sensor manufacturing method as claimed in claim 9, wherein
after said step of removing said sacrifice layer on said inner side through said hole, form in sequence a first insulation layer and a connection layer on said conduction wiring layer, to seal off said hole, then perform step of forming said patterned via in said silicon substrate; and
in said step of forming said conduction wiring layer on said sacrifice layer and connecting it electrically to said silicon substrate, it further comprises following step:
form a first metal layer on said sacrifice layer, to connect it electrically to said silicon substrate;
at a position corresponding to said sacrifice layer inside said first metal layer, form at least an opening in said first metal layer, to expose said sacrifice layer, and form a second insulation layer to fill said opening; and
form a metal wiring layer having said hole on said first metal layer and said second insulation layer, so as to form said conduction wiring layer on said sacrifice layer.
11. The sensor manufacturing method as claimed in claim 10, wherein
in said step of forming said metal wiring layer on said first metal layer and said second insulation layer, form a first insulation block on said second insulation layer, form a second insulation block and a metal block on said first metal layer, said first insulation block and said second insulation block are adjacent to said metal block, and are located respectively inside and outside said metal block, form a second metal layer having said hole on said first insulation block, said second insulation block, and said metal block, and form a third insulation layer in said hole to be located on said first insulation block, so that said metal wiring layer is formed on said first metal layer and said second insulation layer;
in said step of removing said sacrifice layer inside said conduction wiring layer through said hole, remove said third insulation layer, said first insulation block, said second insulation layer, said sacrifice layer on inner side of said first metal layer; and
in said step of removing said part of said sacrifice layer to expose said silicon substrate, remove said part of said sacrifice layer to expose said silicon substrate, so that
said sacrifice layer has a first sacrifice block and a second sacrifice block, and said second sacrifice block is on an outer perimeter of said first sacrifice block, such that said first sacrifice block is made of silicon dioxide, while said second sacrifice block is made of silicon dioxide, silicon carbide, or undoping polysilicon.
12. The sensor manufacturing method as claimed in claim 9, wherein said patterned via is formed through deep reactive-ion etching, and said sacrifice layer is formed by using thermal oxidation method or plasma enhanced chemical vapor deposition (PECVD), in said step of removing said sacrifice layer in said patterned via through said hole, use Hydrogen Fluoride (HF) vapor through said hole, or utilize wet etching through said hole; and after said step of forming said pattern via in said silicon substrate, at least a circuit chip is fixed onto said silicon substrate by means of hermetic bonding.
13. A microphone structure, comprising:
a silicon substrate, provided with an opening; and
a silicon layer, disposed on said silicon substrate, said silicon layer includes at least a first silicon block and at least a second silicon block for performing gap-closing sensing, said first silicon block is used as a diaphragm, and said first silicon block and said second silicon block are separated by at least two different co-planar gaps connecting with said opening.