1. A device, comprising:
a functional circuit, said functional circuit comprising:
a logic circuit; and
a variable delay; and
a latch;
wherein
said variable delay is coupled to receive input from a data path and coupled to provide output to the latch; and
said latch is coupled to receive input from the variable delay and provide input to said logic circuit; and
a control circuit, said control circuit comprising:
a register;
a repeater;
a comparator; and
a command detector;
wherein
said register is coupled to receive input from a first external source and coupled to provide output to said repeater and said comparator;
said repeater is coupled to receive input from said register and said command detector and to provide output to a second external source;
said command detector is coupled to receive input from said second external source and to provide output to said repeater and said comparator; and
said comparator is coupled to receive input from said latch of said functional circuit and said register and provide output to control said variable delay.
2. The device of claim 1, wherein said device is a memory device and said logic circuit comprise a memory array.
3. The device of claim 2, wherein said memory array comprises a plurality of dynamic random access memory (DRAM) cells.
4. The device of claim 1, wherein said first external source is a register coupled to said device and said second external source is a bus coupled to said device.
5. The device of claim 4, wherein said device is a memory controller and said logic circuit comprise a control logic for controlling a memory device.
6. The device of claim 5, wherein said control logic is capable of operating a dynamic random access memory (DRAM) device.
7. A system, comprising:
a bus;
a pattern register;
a first device, said first device coupled to said bus and said first device comprising:
a first functional circuit, said first functional circuit comprising:
a first logic circuit; and
a first variable delay; and
a first latch;
wherein
said first variable delay is coupled to receive input from a data path and coupled to provide output to the first latch; and
said first latch is coupled to receive input from the first variable delay and provide input to said first logic circuit; and
a first control circuit, said first control circuit comprising:
a first register;
a first repeater;
a first comparator; and
a first command detector;
wherein
said first register is coupled to receive input from said pattern register and coupled to provide output to said repeater and said first comparator;
said first repeater is coupled to receive input from said first register and said command detector and to provide output to said bus;
said first command detector is coupled to receive input from said bus and to provide output to said repeater and said first comparator; and
said first comparator is coupled to receive input from said latch of said first functional circuit and said first register and provide output to control said first variable delay; and
a second device, said second device coupled to the bus and said second device comprising:
a second functional circuit, said second functional circuit comprising:
a second logic circuit; and
a second variable delay; and
a second latch;
wherein
said second variable delay is coupled to receive input from the data path and coupled to provide output to the second latch; and
said second latch is coupled to receive input from the second variable delay and provide input to said second logic circuit; and
a second control circuit, said second control circuit comprising:
a second register;
a second repeater;
a second comparator; and
a second command detector;
wherein
said second register is coupled to receive input from said bus and coupled to provide output to said repeater and said second comparator;
said second repeater is coupled to receive input from said second register and said command detector and to provide output to said bus;
said second command detector is coupled to receive input from said bus and to provide output to said repeater and said second comparator; and
said second comparator is coupled to receive input from said latch of said second functional circuit and said second register and provide output to control said second variable delay.
8. The system of claim 7, wherein said first device is a memory controller.
9. The system of claim 7, wherein said second device is a memory device.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.
1. An integrated circuit, comprising:
a first macro circuit block having an input;
a second macro circuit block having an input;
a first configurable delay circuit having an output connected to the input of the first macro circuit block;
a second configurable delay circuit having an output connected to the input of the second macro circuit block; and
a signal distribution network having an output connected to an input of the first configurable delay circuit;
wherein the first configurable delay circuit and the second configurable delay circuit have a same footprint, but have different delay characteristics.
2. The integrated circuit of claim 1, wherein the output of the signal distribution network is connected to an input of the second configurable delay circuit.
3. The integrated circuit of claim 1, wherein the signal distribution network is a clock signal distribution network, and wherein the input of the first macro circuit block is a clock input.
4. The integrated circuit of claim 1, wherein the signal distribution network is a data signal distribution network, and wherein the input of the first macro circuit block is a data input.
5. The integrated circuit of claim 1, wherein the first and second configurable delay circuits each comprise a chain of buffers, wherein a number of buffers in the chain of buffers is the same in the first and second configurable delay circuits.
6. The integrated circuit of claim 5, wherein a total delay for a given one of the first and second configurable delay circuits is based on a number of buffers in the chain of buffers, which are serially connected between an input and output of the given configurable delay circuit.
7. The integrated circuit of claim 1, further comprising a third configurable delay circuit having footprint that is different than the footprints of the first and second configurable delay circuits.
8. The integrated circuit of claim 7, further comprising a third macro circuit block having an input connected to an output of the third configurable delay circuit.
9. The integrated circuit of claim 7, wherein an output of the third configurable delay circuit is connected to an input of the second configurable delay circuit.
10. The integrated circuit of claim 9, wherein an input of the third configurable delay circuit is connected to an output of the signal distribution network.
11. A chip package comprising the integrated circuit of claim 1.
12. An integrated circuit, comprising:
a macro circuit block having an input;
a signal distribution network having an output; and
a chain of configurable delay circuits serially connected between the input of the macro circuit block and the output of the signal distribution network;
wherein the plurality of configurable delay circuits comprises at least a first configurable delay circuit and a second configurable delay circuit, which have a same footprint, but have different delay characteristics.
13. The integrated circuit of claim 12, wherein the signal distribution network is a clock signal distribution network, and wherein the input of the macro circuit block is a clock input.
14. The integrated circuit of claim 12, wherein the signal distribution network is a data signal distribution network, and wherein the input of the macro circuit block is a data input.
15. The integrated circuit of claim 12, wherein the first and second configurable delay circuits each comprise a chain of buffers, wherein a number of buffers in the chain of buffers is the same in the first and second configurable delay circuits.
16. The integrated circuit of claim 15, wherein a total delay for a given one of the first and second configurable delay circuits is based on a number of buffers in the chain of buffers, which are serially connected between an input and output of the given configurable delay circuit.
17. The integrated circuit of claim 12, wherein the chain of configurable delay circuits further comprises a third configurable delay circuit having footprint that is different than the footprints of the first and second configurable delay circuits.
18. A chip package comprising the integrated circuit of claim 12.
19. An integrated circuit, comprising:
a macro circuit block having an input;
a signal distribution network having an output; and
a chain of configurable delay circuits serially connected between the input of the macro circuit block and the output of the signal distribution network;
wherein the plurality of configurable delay circuits comprises at least a first configurable delay circuit and a second configurable delay circuit, which have different footprints, but have the same delay characteristics.
20. A chip package comprising the integrated circuit of claim 19.