1. A radio frequency communication system for communicating radio frequency data signals containing data to and from remotely located data devices, said system comprising:
a radiating transmission line;
a head end unit comprising a system server, said head end unit being coupled to a first end of the radiating transmission line; and
at least one regeneration amplifier connected to said transmission line for amplifying the data signals by demodulating the data signals to recover the data contained therein and modulating the recovered data into a regenerated radio frequency data signal containing the recovered data, said regeneration amplifier comprising:
a demodulator for demodulating the data signals to recover the data contained therein;
a modulator for modulating the recovered data into a regenerated radio frequency data signal containing the recovered data; and
a processor connected to the modulator and demodulator for receiving the recovered data from the demodulator and performing error detection and correction functions on the recovered data prior to modulating the recovered data,
wherein the regenerated data signal is transmitted through the radiating transmission line at a power level permitting transmission and radiation of the regenerated radio frequency data signal to the remotely located data devices within a coverage area of the regeneration amplifier.
2. The communication system as defined in claim 1 wherein the regeneration amplifier further comprises: a device for tracking the data devices within the coverage area of the regeneration amplifier; wherein the regeneration amplifier periodically transmits information regarding the data devices within its coverage area to the system server of the base unit to permit the system server to account for delays resulting from the regeneration amplifiers.
3. The communication system as defined in claim 2 wherein each data device in the communication system has a unique address which can be transmitted through the communication system to the regeneration amplifiers; wherein the device for tracking the data devices monitors the unique addresses being transmitted by data devices to track the data devices within the coverage area; and wherein the device to track the data devices periodically transmits the unique addresses of the data devices within the coverage area to the system server to permit the system server to account for delays caused by the regeneration amplifier.
4. The communication system as defined in claim 2 wherein the system server determines a number of regenerations required for a data signal to reach a target data device and for an acknowledgement signal to be received by the system server so that the system server can account for delays caused by each regeneration amplifier when sending radio frequency data signals through the radiating transmission line and awaiting an acknowledgement signal from the data device to which the radio frequency data signals were sent.
5. The communication system as defined in claim 4 wherein the system server comprises a topology of the system and the system server accounts for delays caused by each regeneration by determining the location of the target data device in the topology and calculating the number of regenerations required to send a data signal to the target device and receive an acknowledgement.
6. The communication system as defined in claim 4 wherein the data signals have a frequency of between 2 MHz and 200 MHz and a bandwidth of 0.5 MHz to 32 MHz.
7. The communication system as defined in claim 4 wherein the system server accounts for delays in sending data signals and receiving acknowledgement signals so as to comply with DOCSIS.
8. The communication system as defined in claim 1 wherein the head end unit transmits data signals to the radiating transmission line at a first frequency and receives data signals from the radiating transmission line at a second frequency; wherein the demodulator of each regeneration amplifier comprises a first demodulator for demodulating the radio frequency data signals at the first frequency travelling from the system server, and, a second demodulator for demodulating the data signals at the second frequency travelling towards the system server; and wherein said modulator comprises a first modulator for modulating the recovered data of data signals travelling from the system server into a first regenerated radio frequency data signal having the first frequency and a power level permitting transmission and radiation of the first regenerated radio frequency data signal, and, a second modulator for modulating the recovered data from data signals travelling towards the system server into a second regenerated radio frequency data signal having the second frequency and a power level permitting transmission of the second regenerated radio frequency data signal.
9. The communication system as defined in claim 1 further comprising: at least one linear amplifier connected to said radiating transmission line for amplifying data signals by filtering the data signals and then amplifying the data signals in a direction of travel.
10. In a radio frequency communication system for communicating radio frequency data signals containing data to and from remotely located data devices through a radiating transmission line, a regeneration amplifier for amplifying the digital signals through the radiating transmission line, said regeneration amplifier comprising:
a demodulator for demodulating the data signals to recover the data contained therein;
a modulator for modulating the recovered data into a regenerated radio frequency data signal containing the recovered data;
an amplifier for amplifying the regenerated data signal for transmission through the radiating transmission line at a power level permitting transmission and radiation of the regenerated radio frequency data signal to the remotely located data devices within a coverage area of the regeneration amplifier; and
a processor connected to the modulator and demodulator for receiving said recovered data from the demodulator and performing error detection and correction functions on the recovered data prior to modulating the recovered data.
11. The regeneration amplifier as defined in claim 10 further comprising:
a device for tracking the data devices within the coverage area of the regeneration amplifier;
wherein the regeneration amplifier periodically transmits information regarding the data devices within the coverage area to a system server to permit the system server to account for delays caused by the demodulator, the error detection and correction functions of the processor, and the modulator.
12. The regeneration amplifier as defined in claim 11 wherein each data device in the communication system has a unique address which can be transmitted through the communication system to the regeneration amplifier; wherein the device for tracking the data devices monitors the unique addresses being transmitted by data devices to track the data devices within the coverage area; and wherein the device to track the data devices periodically transmits the unique addresses of the data devices within the coverage area of the regeneration amplifier to the system server to permit the system server to account for delays caused by the regeneration amplifier.
13. The regeneration amplifier as defined in claim 12 wherein each regeneration amplifier within the communication system has a unique address; and wherein the device for tracking the data devices within the coverage area of the regeneration amplifier periodically sends a control signal to the system server containing the unique address of the regeneration amplifier and the unique address of each data device within the coverage area of the regeneration amplifier.
14. The regeneration amplifier as defined in claim 13 wherein the information regarding the devices within the coverage area of each regeneration amplifier is sent to the system server, so that the system server can determine a number of regenerations required for a data signal to reach a target data device and for an acknowledgement signal to be received by the system server from the target device to permit the system server to account for delays caused by the regeneration amplifiers.
15. The regeneration amplifier as defined in claim 11 wherein the radio frequency communication system comprises a head end unit located at a first end of the radiating transmission line, said head end unit being associated with the system server for transmitting data signals to the transmission lines at a first frequency and for receiving the data signals from the radiating transmission line at a second frequency.
16. The regeneration amplifier as defined in claim 11 wherein the demodulator comprises a first demodulator for demodulating the radio frequency data signals at the first frequency travelling from the system server, and, a second demodulator for demodulating the data signals at the second frequency travelling towards the system server; and wherein said modulator comprises a first modulator for modulating the recovered data of data signals travelling from the system server into a first regenerated radio frequency data signal having the first frequency and a power level permitting transmission and radiation of the first regenerated radio frequency data signal, and, a second modulator for modulating the recovered data from data signals travelling towards the system server into a second regenerated radio frequency data signal having the second frequency and a power level permitting transmission of the second regenerated radio frequency data signal.
17. The regeneration amplifier as defined in claim 16 further comprising first bandpass filters connected between the first demodulator and the radiating transmission line and between the first modulator and the radiating transmission line for filtering the first data signals at the first frequency; and second bandpass filters connected between the second demodulator and the radiating transmission line and between the second modulator and the radiating transmission line for filtering the second data signals at the second frequency.
18. The regeneration amplifier as defined in claim 17 wherein the first radio frequency data signals have a first bandwidth between 0.5 MHz and 32 MHz and the first bandpass filters filter data signals have the first bandwidth at the first frequency.
19. The regeneration amplifier as defined in claim 18 wherein the communication system communicates narrow band signals having a bandwidth of between 10 KHz and 100 KHz at a third frequency travelling away from the head end unit and at a fourth frequency travelling towards the head end unit; wherein the regeneration amplifier further comprises linear amplifiers for amplifying the narrow band frequencies away from the head end unit at the third frequency and towards the head end unit at the fourth frequency; and wherein the regeneration amplifier further comprises third filters located between the linear amplifier and the radiating transmission line for filtering narrow band data signals having the third frequency and fourth filters located between the linear amplifier and the radiating transmission line for filtering narrow band data signals having the fourth frequency.
20. The system as defined in claim 8 wherein the remotely data devices comprise a transceiver for receiving the first regenerated radio frequency data signal radiated by radiating transmission line and for transmitting the second radio frequency data signal to the radiating transmission line.
21. The system as defined in claim 8 wherein the remotely data devices can releasably connect to an interface connected to the radiating transmission for receiving the first regenerated radio frequency data signal from the radiating transmission line and for sending the second radio frequency data signal to the radiating transmission line.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A device comprising:
a transistor; and
two interdigital capacitors,
the transistor being located on an imaginary extension line aligned with a common electrode of the two interdigital capacitors, the common electrode being connected to one of electrode regions of the transistor.
2. The device according to claim 1, wherein the common electrode has a straight line connected to said one of electrode regions of the transistor.
3. The device according to claim 1, wherein the common electrode is connected to said one of electrode regions of the transistor via a straight interconnection line that continues to the common electrode.
4. The device according to claim 1, wherein the two interdigital capacitors comprise:
the common electrode having a bus line and electrode fingers running from the bus line in first and second directions;
a first comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the first direction; and
a second comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the second direction,
the electrode regions of the transistor being located on the imaginary extension line aligned with the bus line of the common electrode.
5. The device according to claim 1, wherein the two interdigital capacitors comprise:
the common electrode having a bus line and electrode fingers running from the bus line in first and second directions;
a first comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the first direction; and
a second comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the second direction,
the bus line of the common electrode being connected to said one of the electrode regions of the transistor via a straight interconnection line that continues to the bus line.
6. The device according to claim 1, wherein the two interdigital capacitors comprise:
the common electrode having a bus line and electrode fingers running from the bus line in first and second directions;
a first comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the first direction; and
a second comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the second direction,
the bus line of the common electrode being connected to a first electrode region of the transistor that corresponds to said one of the electrode regions,
the first comb-like electrode being connected to a second electrode region of the transistor, and
the second comb-like electrode being connected to a control terminal of the transistor.
7. The device according to claim 1, wherein:
the common electrode has a bus line and electrode fingers that run in two directions; and
two electrode regions of the transistor including said one of the electrode regions being located on an imaginary extension line aligned with the bus line.
8. The device according to claim 1, wherein the transistor is close to electrode fingers that run from both sides of a bus line of the common electrode and are arranged in a line.
9. The device according to claim 1, wherein the two interdigital capacitors comprise:
the common electrode having a bus line connected to a first electrode region of the transistor that corresponds to said one of the electrode regions and first and second electrode fingers that run from the bus line in first and second directions;
a first comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the first direction;
a second com-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the second direction;
a first interconnection line connecting the first comb-like electrode to a second electrode region of the transistor; and
a second interconnection line connecting the second comb-like electrode to a control terminal of the transistor.
10. The device according to claims 9, wherein the electrode fingers that run from the bus line include electrode fingers that are close to and in parallel with the first and second interconnection lines so that the first and second interconnection lines can make a capacitance.
11. The device according to claim 10, wherein at least one of the first and second interconnection lines has a crank portion that is located close to the transistor and enables the first and second interconnection lines to be spaced apart from the electrode fingers close to the first and second interconnection lines by an identical distance.
12. The device according to claim 1, wherein the two interdigital capacitors comprise:
the common electrode having a bus line, m (m is a natural number) electrode fingers running from the bus line in a first direction, and n (n is a natural number and is not equal to m) electrode fingers running from the bus line in a second direction;
a first comb-like electrode having electrode fingers alternately arranged with the m electrode fingers; and
a second comb-like electrode having electrode fingers alternately arranged with the n electrode fingers,
the bus line being connected to said one of the electrode regions of the transistor.
13. The device according to claim 1, wherein the two interdigital capacitors comprise:
the common electrode having a bus line connected to a first electrode region of the transistor that corresponds to said one of the electrode regions, and first and second electrode fingers that run from the bus line in first and second directions;
a first comb-like electrode having electrode fingers alternately arranged with the m electrode fingers; and
a second comb-like electrode having electrode fingers alternately arranged with the n electrode fingers,
the electrode fingers running in the first direction having a length different from that of the electrode fingers running in the second direction.
14. The device according to claim 1, wherein:
one of the two interdigital capacitors is connected between a gate and source of the transistor, and the other interdigital capacitor is connected between a drain and source of the transistor; and
the transistor and the two interdigital capacitors form an oscillator.
15. A device comprising:
first and second transistors;
first and second interdigital capacitors connected to the first transistor; and
third and fourth interdigital capacitors connected to the second transistor,
wherein:
the first transistor being located on an imaginary extension line continuing to a first common electrode of the first and second interdigital capacitors;
the second transistor being located on an imaginary extension line continuing to a second common electrode of the third and fourth interdigital capacitors; and
the second and third interdigital capacitors are formed by a third common electrode.
16. The device according to claim 15, wherein the first and second common electrodes have symmetry about the third common electrode.
17. The device according to claim 15, wherein the first and second common electrodes have symmetry about the third common electrode, and the first and second transistors have symmetry with respect to the third common electrode.
18. The device according to claim 15, wherein
the first common electrode has a straight bus line connected to an electrode region of the first transistor; and
the second common electrode has another straight bus line connected to an electrode region of the second transistor.
19. The device according to claim 15, wherein:
the first common electrode has a straight bus line connected to one of two electrode regions of the first transistor;
the second common electrode has another straight bus line connected to one to two electrode regions of the second transistor; and
the other electrode regions of the first and second transistors are connected via a straight interconnection line.
20. The device according to claim 15, wherein:
the first, second and third common electrodes respectively have bus lines;
electrode fingers run from each of the bus lines in first and second directions;
the electrode fingers that run from the bus line of the first common electrode in the second direction are alternately arranged with the electrode fingers that run from the bus line of the third common electrode in the first direction so that the second interdigital capacitor can be made;
the electrode fingers that run from the bus line of the third common electrode in the second direction are alternately arranged with the electrode fingers that run from the bus line of the second common electrode in the first direction so that the third interdigital capacitor can be made.
21. The device according to claim 15, wherein the first and second transistors and the first through fourth capacitors are elements of an oscillator.
22. The device according to claim 15, wherein the first and second transistors and the first through fourth capacitors are formed on a chip.
23. A device comprising:
first and second transistors;
first and second interdigital capacitors connected to the first transistor; and
third and fourth interdigital capacitors connected to the second transistor,
wherein:
the second and third interdigital capacitors have a first common electrode including a straight bus line; and
the first transistor and the first and second interdigital capacitors, and the second transistor and the third and fourth interdigital capacitors have symmetry about the first common electrode.
24. The device according to claim 23, wherein:
electrode regions of the first transistor are located on an imaginary extension line continuing to a second common electrode of the first and second interdigital capacitors; and
electrode regions of the second transistor are located on another imaginary extension line continuing to a third common electrode of the third and fourth interdigital capacitors.
25. The device according to claim 23, wherein the first and second transistors are connected via a straight interconnection line.
26. The device according to claim 23, wherein the first and second transistors and the first through fourth capacitors are elements of an oscillator.
27. The device according to claim 23, wherein the first and second transistors and the first through fourth capacitors are formed on a chip.
28. A device comprising:
first and second transistors;
first and second interdigital capacitors connected to the first transistor; and
third and fourth interdigital capacitors connected to the second transistor,
wherein:
the first and second interdigital capacitors have a first common electrode including a first straight bus line;
the third and fourth interdigital capacitors have a second common electrode including a second straight bus line; and
the first and second bus lines are arranged in a line.
29. The device according to claim 28, wherein the first and second transistors are close to each other and are located between the first and second common electrodes.
30. The device according to claim 28, wherein electrode regions of the first transistor and those of the second transistor are arranged on an imaginary line that connects the first and second common electrodes.
31. The device according to claim 28, wherein:
the first and second capacitors have electrode fingers that run from both sides of the first common electrode and are close to the first transistor; and
the third and fourth capacitors have electrode fingers that run from both sides of the second common electrode and are close to the second transistor.
32. The device according to claim 28, wherein the first and second transistors and the first through fourth capacitors are elements of an oscillator.
33. The device according to claim 28, wherein the first and second transistors and the first through fourth capacitors are formed on a chip.
34. A device comprising:
first and second transistors;
first and second interdigital capacitors connected to the first transistor; and
third and fourth interdigital capacitors connected to the second transistor,
wherein:
the first and second interdigital capacitors have a first common electrode including a first straight bus line;
the third and fourth interdigital capacitors have a second common electrode including a second straight bus line; and
a first circuit pattern including the first transistor and the first and second interdigital capacitors and a second circuit pattern including the second transistor and the third and fourth interdigital capacitors have axial symmetry.
35. The device according to claim 34, wherein the first and second transistors and the first through fourth capacitors are elements of an oscillator.
36. The device according to claim 34, wherein the first and second transistors and the first through fourth capacitors are formed on a chip.
37. A communication device comprising:
a circuit that processes a transmit or receive signal in synchronism with an oscillation signal; and
a device supplying the circuit with the oscillation signal,
the device comprising:
a transistor; and
two interdigital capacitors,
the transistor being located on an imaginary extension line aligned with a common electrode of the two interdigital capacitors, the common electrode being connected to one of electrode regions of the transistor.