1. Form P-1 of 1-(4-benzoyl-piperazin-1-yl)-2-4-methoxy-7-(3-methyl-1,2,4triazol-1-yl)-1H-pyrrolo2,3-cpyridin-3-yl-ethane-1,2-dione characterized by an X-ray powder diffraction pattern in accordance with that shown in FIG. 1.
2. Form P-1 of 1-(4-benzoyl-piperazin-1-yl)-2-4-methoxy-7-(3-methyl-1,2,4triazol-1-yl)-1H-pyrrolo2,3-cpyridin-3-yl-ethane-1,2-dione characterized by an X-ray powder diffraction pattern comprising two or more 20 values selected from the group consisting of: 8.90\xb10.10, 11.21\xb10.10, 16.91\xb10.10 and 21.00\xb10.10.
3. Form P-1 according to claim 1 or 2 wherein the 1-(4-benzoyl-piperazin-1-yl)-2-4-methoxy-7-(3-methyl-1,2,4triazol-1-yl)-1H-pyrrolo2,3-cpyridin-3-yl-ethane-1,2-dione is substantially pure.
4. Form P-1 according to claim 3, wherein substantially pure is greater than 90 percent pure.
5. Form P-1 of 1-(4-benzoyl-piperazin-1-yl)-2-4-methoxy-7-(3-methyl-1,2,4triazol-1-yl)-1H-pyrrolo2,3-cpyridin-3-yl-ethane-1,2-dione characterized by a differential scanning calorimetry (DSC) thermogram in accordance with that shown in FIG. 2.
6. Form P-1 of 1-(4-benzoyl-piperazin-1-yl)-2-4-methoxy-7-(3-methyl-1,2,4triazol-1-yl)-1H-pyrrolo2,3-cpyridin-3-yl-ethane-1,2-dione characterized by a thermo gravimetric analysis (TGA) diagram in accordance with that shown in FIG. 3.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed as new and desired to be protected by Letters Patent of the United States is:
1. A memory device comprising:
a first memory bank including a plurality of memory blocks arranged in horizontal and vertical strips, each of said horizontal strips of memory blocks being divided into a plurality of segments, each of said plurality of memory blocks including a plurality of rows of primary memory cells and at least one row of redundant memory cells;
a plurality of wordlines for accessing said primary and redundant memory cells of said memory blocks, each of said plurality of wordlines being driven by a respective one of a plurality of drivers; and
circuitry for selectively disabling a respective driver for a wordline associated with a row of primary memory cells in which a defective memory cell is located in one of said segments and enabling a respective driver for a wordline associated with a row of redundant memory cells to substitute said row of redundant memory cells for said row of primary memory cells in only said one segment in which said defective memory cell is located.
2. The memory device according to claim 1, wherein at least one of said segments spans at least two adjacent vertical strips of said memory blocks.
3. The memory device according to claim 1, wherein said circuitry further comprises:
a plurality of logic gates, each of said plurality of logic gates having an output coupled to an associated wordline driver,
wherein said respective driver for a wordline associated with a row of primary memory cells is disabled based on said output of one of said plurality of logic gates, and said respective driver for a wordline associated with a row of redundant memory cells is enabled based on said output of another of said plurality of logic gates.
4. The memory device according to claim 3, wherein said respective driver for said wordline associated with said row of redundant memory cells is enabled and said respective driver for said wordline associated with said row of primary memory cells in which said defective memory cell is located is disabled is further based on a portion of an address of said defective memory cell.
5. The memory device according to claim 3, wherein each of said plurality of logic gates is an AND gate having a first input coupled to one of a plurality of first control signals and a second input coupled to one of a plurality of second control signals.
6. The memory device according to claim 5, wherein said plurality of first control signals are respective phase signals.
7. The memory device according to claim 6, further comprising:
a global driver circuit to provide said respective phase signals.
8. The memory device according to claim 6, wherein said respective phase signals are determined based on an address of a memory cell being accessed.
9. The memory device according to claim 6, wherein said plurality of second control signals includes a redundant match signal and a signal complementary to said redundant match signal.
10. The memory circuit according to claim 9, further comprising:
a matching circuit to compare an input memory cell address to an address of said defective memory cell, and if said input memory cell address matches said address of said defective memory cell, outputting a high signal for said redundant match signal and a low signal for said signal complementary to said redundant match signal.
11. The memory device according to claim 10, wherein said high signal for said redundant match signal will enable said respective driver for said wordline associated with said row of redundant memory cells and said low signal for said signal complementary to said redundant match signal will disable said respective driver for said wordline associated with said row of primary memory cells in which said defective memory cell is located.
12. The memory device according to claim 11, further comprising:
logic circuitry to provide said high signal and said low signal to only wordline drivers in said segment in which said defective memory cell is located.
13. The memory device according to claim 10, wherein said matching circuit further comprises:
a plurality of programmable elements to store said address of said defective memory cell.
14. The memory device according to claim 13, wherein said programmable elements are fuses.
15. The memory device according to claim 1, wherein said circuitry further selectively disables a respective driver for a wordline associated with a row of primary cells in which a second defective memory cell is located in a second of said segments and enables a respective driver for a wordline associated with a row of redundant memory cells in said second segment to substitute a portion of said row of redundant memory cells in said second segment for said row of primary memory cells in said second segment in which said second defective memory cell is located.
16. A memory circuit for repairing a portion of a row of memory blocks of a semiconductor memory device, each of said plurality of memory blocks having a corresponding plurality of rows of primary memory cells and at least one row of redundant memory cells, each of said plurality of rows of primary memory cells and said at least one row of redundant memory cells having an associated wordline driven by a respective one of a plurality of drivers, said memory circuit comprising:
a first circuit to compare an input address of a memory cell to be accessed in said memory device with addresses of defective memory cells in said memory device and output a pair of complementary control signals based on said comparison;
a second circuit to provide a plurality of phase signals based on said input address of said memory cell to be accessed; and
a plurality of logic gates, each of said plurality of logic gates having an output connected to one of said plurality of drivers, a first input connected to a respective one of said plurality of phase signals, and a second input connected to one of said pair of complementary control signals,
wherein if said input address of said memory cell to be accessed matches an address of a defective memory cell, said pair of complementary control signals and said plurality of phase signals cause said plurality of logic gates to selectively disable a driver for a respective row of primary memory cells of a memory block in said row of memory blocks in which said defective memory cell is located and enable a driver for said at least one row of redundant memory cells in said memory block to substitute said at least one row of redundant memory cells for said row of primary memory cells in said memory block, without substituting for a corresponding row of primary cells in at least one other of said plurality of memory blocks.
17. The semiconductor memory according to claim 16, wherein said plurality of logic gates are AND gates.
18. The semiconductor memory according to claim 16, wherein said plurality of phase signals includes four phase signals.
19. A memory device comprising:
a memory array comprising at least one row of primary memory cells;
at least one primary row wordline for accessing said primary memory cells, said at least one primary row wordline being divided into a plurality of segments, each of which accesses a respective portion of said primary memory cells;
at least one row of redundant memory cells;
at least one redundant row wordline for accessing said redundant memory cells, said at least one redundant row wordline being divided into a plurality of segments, each of which accesses a portion of said redundant memory cells; and
a programmable logic circuit which can be selectively programmed to replace at least one of said primary row wordline segments associated with a defective memory cell with a redundant row wordline segment during memory access operation.
20. The memory device according to claim 19, wherein said programmable logic circuit further comprises:
a plurality of AND gates, each of said plurality of AND gates having a first input coupled to receive one of a plurality of first control signals, a second input coupled to receive on of a plurality of second control signals, and an output coupled to a driver associated with a respective one of said at least one primary row wordline and said at least one redundant row wordline.
21. The memory device according to claim 20, wherein said plurality of first control signals are respective phase signals.
22. The memory device according to claim 20, further comprising:
a matching circuit to compare an input memory cell address to an address of said defective memory cell and output said plurality of second control signals based on said comparison.
23. A processor system comprising:
a central processing unit; and
a memory device connected to said processing unit to receive data from and supply data to said central processing unit, said memory device comprising:
a first memory bank including a plurality of memory blocks arranged in horizontal and vertical strips, each of said horizontal strips of memory blocks being divided into a plurality of segments, each of said plurality of memory blocks including a plurality of rows of primary memory cells and at least one row of redundant memory cells;
a plurality of wordlines for accessing said primary and redundant memory cells of said memory blocks, each of said plurality of wordlines being driven by a respective one of a plurality of drivers; and
circuitry for selectively disabling a respective driver for a wordline associated with a row of primary memory cells in which a defective memory cell is located in one of said segments and enabling a respective driver for a wordline associated with a row of redundant memory cells to substitute said row of redundant memory cells for said row of primary memory cells in only said one segment in which said defective memory cell is located.
24. The processor system according to claim 23, wherein at least one of said segments spans at least two adjacent vertical strips of said memory blocks.
25. The processor system according to claim 23, wherein said circuitry further comprises:
a plurality of logic gates, each of said plurality of logic gates having an output coupled to an associated wordline driver,
wherein said respective driver for a wordline associated with a row of primary memory cells is disabled based on said output of one of said plurality of logic gates, and said respective driver for a wordline associated with a row of redundant memory cells is enabled based on said output of another of said plurality of logic gates.
26. The processor system according to claim 25, wherein said respective driver for said wordline associated with said row of redundant memory cells is enabled and said respective driver for said wordline associated with said row of primary memory cells in which said defective memory cell is located is disabled is further based on a portion of an address of said defective memory cell.
27. The processor system according to claim 26, wherein each of said plurality of logic gates is an AND gate having a first input coupled to one of a plurality of first control signals and a second input coupled to one of a plurality of second control signals.
28. The processor system according to claim 27, wherein said plurality of first control signals are respective phase signals.
29. The processor system according to claim 28, further comprising:
a global driver circuit to provide said respective phase signals.
30. The processor system according to claim 28, wherein said respective phase signals are determined based on an address of a memory cell being accessed.
31. The processor system according to claim 28 wherein said plurality of second control signals includes a redundant match signal and a signal complementary to said redundant match signal.
32. The processor system according to claim 31, further comprising:
a matching circuit to compare an input memory cell address to an address of said defective memory cell, and if said input memory cell address matches said address of said defective memory cell, outputting a high signal for said redundant match signal and a low signal for said signal complementary to said redundant match signal.
33. The processor system according to claim 32, wherein said high signal for said redundant match signal will enable said respective driver for said wordline associated with said row of redundant memory cells and said low signal for said signal complementary to said redundant match signal will disable said respective driver for said wordline associated with said row of primary memory cells in which said defective memory cell is located.
34. The processor system according to claim 33, further comprising:
logic circuitry to provide said high signal and said low signal to only wordline drivers in said segment in which said defective memory cell is located.
35. The processor system according to claim 32, wherein said matching circuit further comprises:
a plurality of programmable elements to store said address of said defective memory cell.
36. The processor system according to claim 35, wherein said programmable elements are fuses.
37. The processor according to claim 23, wherein said circuitry further selectively disables a respective driver for a wordline associated with a row of primary cells in which a second defective memory cell is located in a second of said segments and enables a respective driver for a wordline associated with a row of redundant memory cells in said second segment to substitute a portion of said row of redundant memory cells in said second segment for said row of primary memory cells in said second segment in which said second defective memory cell is located.
38. The processor system according to claim 23, wherein said central processing unit and said memory device are on a same chip.
39. A processor system comprising:
a central processing unit; and
a memory device connected to said central processing unit to receive data from and supply data to said central processing unit, said memory device comprising:
a plurality of memory blocks each having a plurality of rows of primary memory cells and at least one row of redundant memory cells, each of said plurality of rows of primary memory cells and said at least one row of redundant memory cells having an associated wordline driven by a respective one of a plurality of drivers; and
a memory circuit for repairing a portion of a row of said plurality of memory blocks, said memory circuit comprising:
a first circuit to compare an input address of a memory cell to be accessed in said memory device with addresses of defective memory cells in said memory device and output a pair of complementary control signals based on said comparison;
a second circuit to provide a plurality of phase signals based on said input address of said memory cell to be accessed; and
a plurality of logic gates, each of said plurality of logic gates having an output connected to one of said plurality of drivers, a first input connected to a respective one of said plurality of phase signals, and a second input connected to one of said pair of complementary control signals,
wherein if said input address of said memory cell to be accessed matches an address of a defective memory cell, said pair of complementary control signals and said plurality of phase signals cause said plurality of logic gates to selectively disable a driver for a respective row of primary memory cells of a memory block in said row of memory blocks in which said defective memory cell is located and enable a driver for said at least one row of redundant memory cells in said memory block to substitute said at least one row of redundant memory cells for said row of primary memory cells in said memory block, without substituting for a corresponding row of primary cells in at least one other of said plurality of memory blocks.
40. The processor system according to claim 39, wherein said plurality of logic gates are AND gates.
41. The processor system according to claim 39, wherein said plurality of phase signals includes four phase signals.
42. The processor system according to claim 39, wherein said central processing unit and said memory device are on a same chip.
43. A processor system comprising:
a central processing unit; and
a memory device connected to said central processing unit to receive data from and supply data to said central processing unit, said memory device comprising:
a memory array comprising at least one row of primary memory cells;
at least one primary row wordline for accessing said primary memory cells, said at least one primary row wordline being divided into a plurality of segments, each of which accesses a respective portion of said primary memory cells;
at least one row of redundant memory cells;
at least one redundant row wordline for accessing said redundant memory cells, said at least one redundant row wordline being divided into a plurality of segments, each of which accesses a portion of said redundant memory cells; and
a programmable logic circuit which can be selectively programmed to replace at least one of said primary row wordline segments associated with a defective memory cell with a redundant row wordline segment during memory access operation.
44. The processor system according to claim 43, wherein said programmable logic circuit further comprises:
a plurality of AND gates, each of said plurality of AND gates having a first input coupled to receive one of a plurality of first control signals, a second input coupled to receive on of a plurality of second control signals, and an output coupled to a driver associated with a respective one of said at least one primary row wordline and said at least one redundant row wordline.
45. The processor system according to claim 44, wherein said plurality of first control signals are respective phase signals.
46. The processor system according to claim 44, further comprising:
a matching circuit to compare an input memory cell address to an address of said defective memory cell and output said plurality of second control signals based on said comparison.
47. A method for repairing out at least one defective memory cell in a memory device, said method comprising:
segmenting a each of a plurality of rows of primary memory cell rows and at least one redundant memory cell row into a plurality of segments such that each segment corresponds to at least two row blocks of said memory device;
disabling a primary memory cell row in only a segment in which said at least one defective memory cell is located;
enabling said at least one redundant memory cell row in said segment; and
repairing out said primary memory cell row with said at least one redundant memory cell row in only said segment in which said at least one defective memory cell is located.
48. The method according to claim 47, wherein said steps of segmenting further comprises:
segmenting each of a plurality of rows of primary memory cell rows and at least one redundant memory cell row into a plurality of segments such that each segment corresponds to at least two adjacent row blocks of said memory device.
49. The method according to claim 47, wherein said step of disabling further comprises:
comparing an input address of a memory cell to an address of said at least one defective memory cell; and
if said input address of a memory cell matches said address of said at least one defective memory cell, providing a first control signal to a first logic circuit, wherein an output of said first logic circuit disables said primary memory cell row in only said segment in which said at least one defective memory cell is located.
50. The method according to claim 49 wherein said first logic circuit is an AND gate, said method further comprising:
inputting said first control signal to a first input of said AND gate;
inputting a first phase signal to a second input of said AND gate, said first phase signal being based in part on said input address; and
providing said output of said AND gate to disable said primary memory cell row in only said segment in which said at least one defective memory cell is located.
51. The method according to claim 50, wherein said step of enabling further comprises:
providing a second control signal to a second logic circuit, said second control signal being complementary to said first control signal, wherein an output of said second logic circuit enables said at least one redundant memory cell row in said segment.
52. The method according to claim 51 wherein said second logic circuit is a second AND gate, said method further comprising:
inputting said second control signal to a first input of said second AND gate;
inputting a second phase signal to a second input of said second AND gate, said second phase signal being based in part on said input address; and
providing said output of said second AND gate to enable said at least one redundant memory cell row in said segment.
53. A method for repairing out a defective memory cell in a memory device, said method comprising:
locating said defective memory cell in said memory device;
identifying a segment of a row of memory blocks in which said defective memory cell is located;
disabling a driver associated with a primary memory cell row in which said defective memory cell is located in only said identified segment;
enabling a driver associated with a redundant memory cell row in only said identified segment; and
repairing out said defective memory cell with said redundant memory cell row in only said identified segment.