1. A motorized damper door assembly comprising:
a damper frame;
a damper door comprising a mounting portion rotatably mounted to said frame; and
a seal member comprising a substantially vertically extending moisture barrier defining a chamber between said mounting portion and said moisture barrier.
2. A damper door assembly in accordance with claim 1, said mounting portion and said moisture barrier forming a reservoir.
3. A damper door assembly in accordance with claim 2 wherein said damper door mounting portion comprises a mounting body and a hollow mounting chamber within said mounting body.
4. A damper door assembly in accordance with claim 3, said moisture barrier located within said mounting body.
5. A damper door assembly in accordance with claim 4, further comprising a door pivot pin, said pivot pin received in said moisture barrier.
6. A damper door assembly in accordance with claim 4, said moisture barrier extending substantially parallel to said mounting body.
7. A damper door assembly in accordance with claim 1 wherein said moisture barrier extends from said damper frame.
8. A motorized damper door assembly comprising:
a damper frame;
a damper door comprising a mounting portion rotatably mounted to said frame; and
a seal member extending from said damper frame and forming a reservoir in said mounting portion.
9. A damper door assembly in accordance with claim 8 wherein said damper door mounting portion comprises a mounting body and a hollow mounting chamber within said mounting body.
10. A damper door assembly in accordance with claim 9, said seal member comprising a substantially vertically extending moisture barrier.
11. A damper door assembly in accordance with claim 10, said moisture barrier located within said mounting body.
12. A damper door assembly in accordance with claim 11, further comprising a door pivot pin, said pivot pin received in said moisture barrier.
13. A damper door assembly in accordance with claim 11, said moisture barrier extending substantially parallel to said mounting body.
14. A damper door assembly in accordance with claim 11 wherein said moisture barrier extends from said door frame.
15. A motorized damper assembly for a refrigerator, said damper assembly comprising:
a damper frame;
a damper door comprising a mounting portion rotatably mounted to said frame;
a seal member comprising a substantially vertically extending moisture barrier extending within said mounting portion; and
a door pivot pin located within said moisture barrier.
16. A damper assembly in accordance with claim 15, said mounting portion and said moisture barrier forming a reservoir.
17. A damper door assembly in accordance with claim 16 wherein said damper door mounting portion comprises a mounting body and a hollow mounting chamber within said mounting body.
18. A damper door assembly in accordance with claim 17, said moisture barrier extending substantially parallel to said mounting body.
19. A damper door assembly in accordance with claim 15 wherein said moisture barrier extends from said door frame.
20. A damper door assembly in accordance with claim 15 further comprising a motor adjacent said door frame and coupled to said door pivot.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for conditionally maintaining a logic level of a node in flip-flop circuit, comprising:
during a first part of a periodic time interval, maintaining said logic level of said node by feeding back to said node said logic level after two inversions; and
during a second part of said periodic interval, not maintaining said logic level of said node by disconnecting said feeding back to said node.
2. The method of claim 1 wherein said flip-flop circuit comprises, a pre-charged stage coupled to an evaluation stage by said node.
3. The method of claim 1 wherein said flip-flop circuit comprises, a pre-charged stage coupled to an evaluation stage and wherein said node is an output of said evaluation stage.
4. The method of claim 1 wherein said flip-flop circuit is a hybrid type flip-flop circuit.
5. The method of claim 1 wherein said flip-flop circuit is a D-type flip-flop circuit.
6. The method of claim 1 wherein said flip-flop circuit comprises, a pre-charged stage coupled to an evaluation stage, and wherein said first part of said periodic time interval, includes a portion of a transparency window.
7. The method of claim 1 wherein said flip-flop circuit comprises, a pre-charged stage coupled to an evaluation stage, and wherein said second part of said periodic time interval, includes a portion of a transparency window.
8. A conditional keeper circuit for conditionally maintaining a logic level of a node in flip-flop circuit, said flip-flop circuit comprising a pre-charged stage coupled to an evaluation stage, said conditional keeper circuit comprising:
an inverter circuit connected to said node;
an inverted tri-state circuit connected to said inverter circuit and to said node; and
a control circuit sending a signal to set said inverted tri-state circuit to a high impedance state for a fixed time period.
9. The method of claim 8 wherein said pre-charged stage is coupled to an evaluation stage by said node.
10. The method of claim 8 wherein said node is an output of said evaluation stage.
11. The system of claim 8 further comprising:
a clock signal;
an inverted clock signal comprising a first output of a first inverter having said clock signal as a first input;
a delayed clock signal comprising a second output of a second inverter having said first output as a second input; and
an inverted delayed clock signal comprising a third output of a third inverter having said second output as a third input.
12. The method of claim 11 wherein said control circuit sends said signal, when said delayed clock signal has a low logic level and said inverted delayed clock signal has a high logic level.
13. The method of claim 11 wherein said control circuit sends said signal, when said delayed clock signal has a low logic level or said inverted delayed clock signal has a high logic level.
14. The method of claim 11 wherein said control circuit sends said signal, when said inverted clock signal has a low logic level and said delayed clock signal has a high logic level.
15. The method of claim 11 wherein said control circuit sends said signal, when said inverted clock signal has a low logic level or said delayed clock signal has a high logic level.
16. A method for reducing delay in a flip-flop, comprising, a pre-charged stage coupled to an evaluation stage by at least an internal node, said method comprising:
disconnecting a first keeping circuit of said pre-charged stage in a part of a transparency window, wherein said first keeping circuit maintains a first logic level on said internal node; and
setting said internal node to a second logic value after said disconnecting said first keeping circuit;
17. The method of claim 16 further comprising:
disconnecting a second keeping circuit of said evaluation stage in said part of said transparency window, wherein said second keeping circuit maintains a third logic level on an output of said evaluation stage; and
setting said output to a fourth logic level based on said second logic value after said disconnecting said second keeping circuit.
18. The method of claim 16 further comprising:
disconnecting a second keeping circuit of said evaluation stage in another part of said transparency window, wherein said second keeping circuit maintains a third logic level on an output of said evaluation stage; and
setting said output to a fourth logic level based on said second logic value after said disconnecting said second keeping circuit.
19. The method of claim 18 wherein said part and said another part are overlapping.
20. The method of claim 16 wherein said flip-flop is a hybrid type flip-flop.
21. The method of claim 20 wherein said hybrid type flip-flop is a D type flip-flop.
22. The method of claim 16 wherein said transparency window comprises a time period, when said internal node is logically equivalent to an inverted value of a data input into said pre-charge stage.
23. A system for improving speed in a hybrid type flip-flop comprising:
a pre-charge stage for determining a pre-charge stage output depending upon a data input during a first part of a transparency window, said pre-charge stage comprising a first conditional keeper for keeping said pre-charge stage output; and
an evaluation stage for evaluating said pre-charge stage output to produce a data output during a second part of said transparency window, said evaluation stage comprising a second conditional keeper for keeping said data output;
wherein when outside of said transparency window either said first conditional keeper is operating like a first unconditional keeper or said second conditional keeper is operating like a second unconditional keeper.
24. The system of claim 23 wherein said pre-charge stage further comprises an nMOS transistor stack, wherein a nMOS transistor for said data input is at a top of said nMOS transistor stack.
25. The system of claim 23 wherein said first conditional keeper includes a plurality of pMOS transistors in series coupled to a plurality of nMOS transistors in series, wherein a pMOS transistor of said plurality of pMOS transistors is part of a conditional control circuit of said first conditional keeper.
26. The system of claim 23 wherein said first conditional keeper includes a plurality of pMOS transistors in series coupled to a plurality of nMOS transistors in series, wherein a pMOS transistor of said plurality of pMOS transistors and a nMOS transistor of said plurality of nMOS transistors are part of a conditional control circuit of said second conditional keeper.
27. The system of claim 23 further comprising:
a clock signal;
an inverted delayed clock signal, wherein said transparency window includes, when said clock signal is at a first high logic level and when said inverted delayed clock signal is at a second high logic level; and
a delayed clock signal for disabling said evaluation stage during said first part of said transparency window, wherein said disabling comprises preventing said evaluation stage from setting said data output to a first low logic level.
28. A method for reducing delay in a flip-flop, comprising, a pre-charged stage coupled to an evaluation stage by at least an internal node, said method comprising:
disconnecting a first keeping circuit of said pre-charged stage in at least a first portion of a transparency window, wherein said first keeping circuit maintains a first logic level on said internal node;
setting said internal node to a second logic value after said disconnecting said first keeping circuit;
disconnecting a second keeping circuit of said evaluation stage in at least a second portion of said transparency window, wherein said second keeping circuit maintains a third logic level on an output of said evaluation stage; and
setting said output to a fourth logic level based on said second logic value after said disconnecting said second keeping circuit.
29. The method of claim 28 wherein said flip-flop is a hybrid type flip-flop.
30. The method of claim 28 wherein said flip-flop is a D type flip-flop.
31. A system for improving performance of a hybrid type flip-flop, comprising:
a pre-charge stage for receiving a data input and setting an internal node; and
an evaluation stage for setting a data output, wherein said evaluation stage is connected to said pre-charge stage by said internal node, wherein said evaluation stage comprises a plurality of NAND gates, and wherein said data output is feedback into a NAND gate of said plurality of NAND gates.
32. The system of claim 31 wherein said hybrid type flip-flop is a D type flip-flop.
33. A method for combining an evaluation stage of a hybrid flip-flop coupled to external digital logic circuitry, wherein said evaluation stage comprises a plurality of NAND gates, said method comprising:
identifying external logic gates in said external digital logic circuitry;
performing a Boolean logic minimization using said external logic gates and said plurality of NAND gates; and
combining said evaluation stage and said external logic gates.
34. The system of claim 33 wherein said external logic gates include another evaluation stage of another hybrid flip-flop.
35. The system of claim 34 wherein said external logic gates further includes at least one logic gate connected to said evaluation stage and to said another evaluation stage.