1. A buffer circuit connectable to a power supply voltage, comprising:
a node;
a driver circuit coupled to the node and comprising at least a first PMOS transistor, the first PMOS transistor having a substrate, a drain, and a parasitic diode between the drain and the substrate, the driver circuit having an on state and an off state;
a first part to provide a first bias to the substrate of the first PMOS transistor when a first signal having a voltage level higher than the power supply voltage appears at the node; and
a second part to provide a second bias to the substrate of the first PMOS transistor when a second signal having a voltage level less than the power supply voltage appears at the node, wherein the second bias has a voltage level approximately equal to the power supply voltage when the driver circuit is in the off state.
2. The circuit of claim 1, wherein the second part comprises an NMOS transistor and a second PMOS transistor coupled to the node, both being turned on when the second signal appears at the node.
3. The circuit of claim 2, further comprising a third PMOS transistor coupled to the node, the NMOS transistor and the second PMOS transistor, wherein the third PMOS transistor is turned on to turn off the NMOS transistor and the second PMOS transistor when the first signal appears at the node, and wherein the third PMOS transistor is turned off when the second signal appears at the node.
4. The circuit of claim 1, wherein the power supply voltage is lower than the voltage level of the first signal.
5. The circuit of claim 1, wherein the voltage level of the second signal is approximately 0V.
6. The circuit of claim 1, wherein the parasitic diode of the first PMOS transistor is off when the buffer circuit is stabilized.
7. The circuit of claim 1, wherein the driver circuit further comprises two stacked NMOS transistors serially coupled to the first PMOS transistor, all of the first PMOS transistor and the two stacked NMOS transistors being off when the driver circuit is in the off state, and either the first PMOS transistor or both of the two stacked NMOS transistors being on when the driver circuit is in the on state.
8. The circuit of claim 1, wherein the first part comprises a second PMOS transistor having a gate, a source, a drain and a substrate, and wherein the gate of the second PMOS transistor is connectable to the power supply voltage, the source of the second PMOS transistor is coupled to the node, and both the drain and substrate of the second PMOS transistor are coupled to the substrate of the first PMOS transistor.
9. The circuit of claim 1, wherein the first bias has a voltage level approximately equal to the voltage level of the first signal.
10. The circuit of claim 1, wherein the second bias has a voltage level approximately equal to the power supply voltage when the driver circuit is in the on state.
11. The circuit of claim 1, wherein the buffer circuit comprises a plurality of PMOS transistors, each having a substrate, and wherein the substrate of each of the plurality of PMOS transistors is coupled to the substrate of the first PMOS transistor.
12. A buffer circuit connectable to a power supply voltage, comprising:
a node;
a driver circuit comprising at least a first PMOS transistor, the first PMOS transistor having a gate, a source and a drain, one of the source and the drain of the first PMOS transistor being coupled to the node;
a first part to provide a first bias to the gate of the first PMOS transistor when a first signal having a voltage level higher than the power supply voltage appears at the node;
a second part to provide a second bias to the gate of the first PMOS transistor when a second signal having a voltage level no greater than the power supply voltage appears at the node, wherein the second part comprises an NMOS transistor and a second PMOS transistor coupled together to provide the second bias voltage to the gate of the first PMOS transistor; and
a third PMOS transistor coupled to the second part to turn off the NMOS transistor and the second PMOS transistor when the first signal appears at the node.
13. The circuit of claim 12, wherein the power supply voltage is lower than the voltage level of the first signal.
14. The circuit of claim 12, wherein the voltage level of the second signal is approximately 0V.
15. The circuit of claim 12, wherein the first part comprises a fourth PMOS transistor coupled to the gate of the first PMOS transistor.
16. The circuit of claim 12, wherein the first bias has a voltage level approximately equal to the voltage level of the first signal.
17. The circuit of claim 12, wherein the second bias has a voltage level approximately equal to the power supply voltage.
18. The circuit of claim 12, further comprising a fourth PMOS transistor coupled to the second PMOS transistor to turn off the second PMOS transistor to prevent a leakage through the second PMOS transistor when the first PMOS transistor is turned on.
19. A buffer circuit connectable to a power supply voltage, comprising:
a node;
a driver circuit coupled to the node comprising at least a first PMOS transistor, the first PMOS transistor having a gate and a substrate, the driver circuit having an on state and an off state;
a first part coupled to the gate and the substrate of the first PMOS transistor to provide a first bias to the gate of the first PMOS transistor and a second bias to the substrate of the first PMOS transistor when a first signal having a voltage level higher than the power supply voltage appears at the node; and
a second part coupled to the gate and the substrate of the first PMOS transistor to provide a third bias to the gate of the first PMOS transistor and a fourth bias to the substrate of the first PMOS transistor when a second signal having a voltage level no greater than the power supply voltage appears at the node, wherein a voltage level of the fourth bias is approximately equal to the power supply voltage when the driver circuit is in the off state.
20. The circuit of claim 19, wherein the power supply voltage is lower than the voltage level of the first signal, wherein the voltage level of the second signal is approximately 0V.
21. The circuit of claim 19, wherein a voltage level of the first bias is approximately equal to the voltage level of the first signal.
22. The circuit of claim 19, wherein a voltage level of the second bias is approximately equal to the voltage level of the first signal.
23. The circuit of claim 19, wherein a voltage level of the third bias is approximately equal to the power supply voltage.
24. The circuit of claim 19, wherein the voltage level of the fourth bias is approximately equal to the power supply voltage when the driver circuit is in the on state.
25. A system, comprising:
a first circuit on a first chip and a second circuit on a second chip;
a buffer circuit on the first chip having an input mode and an output mode of operation and coupled between the first circuit and the second circuit, wherein the buffer circuit is connectable to a first power supply voltage and the second circuit is connectable to a second power supply voltage, and wherein the first power supply voltage is lower than the second power supply voltage;
a node coupling the buffer circuit to the second circuit; and
a control signal terminal for providing a first control signal to switch the buffer circuit into the output mode, in which the buffer circuit receives at least one signal from the first circuit and outputs at least one signal to the second circuit, and for providing a second control signal to switch the buffer circuit into the input mode, in which the buffer circuit receives at least one signal from the second circuit and outputs at least one signal to the first circuit,
wherein the buffer circuit comprises
a driver circuit comprising at least a first PMOS transistor, the first PMOS transistor having a drain and a substrate,
a first part coupled to the substrate of the first PMOS transistor to provide a first bias to the substrate of the first PMOS transistor when a first signal having a voltage level higher than the first power supply voltage appears at the node, wherein the first bias has a voltage level approximately equal to the voltage level of the first signal, and
a second part coupled to the substrate of the first PMOS transistor to provide a second bias to the substrate of the first PMOS transistor when a second signal having a voltage level lower than the first power supply voltage appears at the node, wherein the second bias has a voltage level approximately equal to the first power supply voltage in the input mode.
26. The circuit of claim 25, wherein the second part of the buffer circuit comprises an NMOS transistor and a second PMOS transistor coupled to the node, both being turned on when the second signal appears at the node, wherein each of the NMOS transistor and the second PMOS transistor has a substrate, a source, a drain and a gate, and wherein the gate of the NMOS transistor and one of the source and the drain of the second PMOS transistor are connectable to the first power supply voltage, one of the source and the drain of the NMOS transistor is coupled to the gate of the second PMOS transistor, the other of the source and the drain of the NMOS transistor is coupled to the node, the substrate of the NMOS transistor is grounded, and the substrate and the other of the source and the drain of the second PMOS transistor are coupled to the substrate of the first PMOS transistor.
27. The circuit of claim 26, wherein the buffer circuit further comprises a third PMOS transistor coupled to the node, the NMOS transistor, and the second PMOS transistor, the third PMOS transistor having a gate connectable to the first power supply voltage, a source coupled to the node, a drain coupled to the gate of the second PMOS transistor, and a substrate coupled to the substrate of the first PMOS transistor, wherein the third PMOS transistor is turned on to turn off the NMOS transistor and the second PMOS transistor when the first signal appears at the node, and wherein the third PMOS transistor is turned off when the second signal appears at the node.
28. The circuit of claim 25, wherein the first power supply voltage is lower than the second power supply voltage.
29. The circuit of claim 25, wherein the driver circuit is turned on in the output mode and turned off in the input mode.
30. The circuit of claim 25, wherein the first part of the buffer circuit comprises a second PMOS transistor having a gate, a source, a drain and a substrate, and wherein the gate of the second PMOS transistor is connectable to the first power supply voltage, one of the source and the drain of the second PMOS transistor is coupled to the node, and the other of the source and the drain and the substrate of the second PMOS transistor are coupled to the substrate of the first PMOS transistor.
31. A system, comprising:
a first circuit on a first chip and a second circuit on a second chip;
a buffer circuit on the first chip having an input and an output mode of operation and coupled between the first circuit and the second circuit, wherein the buffer circuit is connectable to a first power supply voltage and the second circuit is connectable to a second power supply voltage, and wherein the first power supply voltage is lower than the second power supply voltage;
a node coupling the buffer circuit to the second circuit; and
a control signal terminal for providing a first control signal to switch the buffer circuit into the output mode, in which the buffer circuit receives at least one signal from the first circuit and outputs at least one signal to the second circuit, and for providing a second control signal to switch the buffer circuit into the input mode, in which the buffer circuit receives at least one signal from the second circuit and outputs at least one signal to the first circuit,
wherein the buffer circuit comprises
a driver circuit comprising at least a first PMOS transistor, the first PMOS transistor having a gate,
a first part to provide a first bias to the gate of the first PMOS transistor when a first signal having a voltage level higher than the power supply voltage appears at the node,
a second part to provide a second bias to the gate of the first PMOS transistor when a second signal having a voltage level no greater than the power supply voltage appears at the node, wherein the second bias has a voltage level approximately equal to the power supply voltage, and wherein the second part comprises an NMOS transistor and a second PMOS transistor coupled together to provide the second bias voltage to the gate of the first PMOS transistor, and
a third PMOS transistor coupled to the second part,
wherein the third PMOS transistor is turned on to turn off the NMOS transistor and the second PMOS transistor when the first signal appears at the node and turned on when the second signal appears at the node.
32. The circuit of claim 31, wherein the first part of the buffer circuit comprises a fourth PMOS transistor coupled to the gate of the first PMOS transistor, and wherein the fourth PMOS transistor is turned on when the first signal appears at the node.
33. The circuit of claim 31, further comprising a fourth PMOS transistor coupled to the second PMOS transistor to turn off the second PMOS transistor when the buffer circuit outputs a logic high signal to the second circuit in the output mode to prevent a leakage through the second PMOS transistor.
34. A system, comprising:
a first circuit on a first chip and a second circuit on a second chip;
a buffer circuit on the first chip having an input and an output mode of operation and coupled between the first circuit and the second circuit, wherein the buffer circuit is connectable to a first power supply voltage and the second circuit is connectable to a second power supply voltage, and wherein the first power supply voltage is lower than the second power supply voltage;
a node coupling the buffer circuit to the second circuit; and
a control signal terminal for providing a first control signal to switch the buffer circuit into the output mode, in which the buffer circuit receives at least one signal from the first circuit and outputs at least one signal to the second circuit, and for providing a second control signal to switch the buffer circuit into the input mode, in which the buffer circuit receives at least one signal from the second circuit and outputs at least one signal to the first circuit,
wherein the buffer circuit comprises
a driver circuit coupled to the node comprising at least a first PMOS transistor, the first PMOS transistor having a gate and a substrate,
a first part of the buffer circuit coupled to the gate and the substrate of the first PMOS transistor to provide a first bias to the gate of the first PMOS transistor and a second bias to the substrate of the first PMOS transistor when a first signal having a voltage level higher than the first power supply voltage appears at the node, and
a second part of the buffer circuit coupled to the gate and the substrate of the first PMOS transistor to provide a third bias to the gate of the first PMOS transistor and a fourth bias to the substrate of the first PMOS transistor when a second signal having a voltage level lower than the first power supply voltage appears at the node.
35. The circuit of claim 34, wherein the voltage level of the first signal is approximately equal to the second power supply voltage and the voltage level of the second signal is approximately 0V.
36. The circuit of claim 34, wherein a voltage level of the first bias and a voltage level of the second bias are approximately equal to the voltage level of the first signal and a voltage level of the third bias and a voltage level of the fourth bias are approximately equal to the first power supply voltage.
37. The circuit of claim 34, wherein the first circuit is connectable to the first power supply voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An optical disk player comprising:
a radio frequency (RF) unit configured to generate an RF signal from information stored on an optical disk;
a defect signal detector configured to generate a defect signal from the RF signal;
an enable unit configured to generate an edge interval value indicating a rotational frequency of the optical disk by checking leading edges of the defect signal and generating a latch pointer signal having a constant period from the edge interval value; and
a decoder configured to generate burst cutting area (BCA) data by decoding the defect signal using the latch pointer signal.
2. The optical disk player of claim 1, wherein the enable unit comprises:
a frequency detector configured to detect edge signals indicating the leading edges, to update the edge interval value indicating the rotational frequency of the optical disk for a respective frame, and to output the updated interval value; and
a latch pointer generator configured to generate the latch pointer signal based on the edge interval value indicating the rotational frequency of the optical disk and to compensate for a location of the latch pointer signal.
3. The optical disk player of claim 1, wherein the rotational frequency of the optical disk is a rotational frequency of the optical disk when the optical disk operates in a constant linear velocity (CLV) mode.
4. The optical disk player of claim 1, wherein the edge interval value indicating the rotational frequency of the optical disk is a maximum edge interval value among interval values between the leading edges in one frame.
5. The optical disk player of claim 1, wherein the edge interval value indicating the rotational frequency of the optical disk is a minimum edge interval value among interval values between the leading edges in one frame.
6. The optical disk player of claim 2, wherein the frequency detector comprises:
an edge detector configured to detect the edge signal, to count the leading edges, and to generate a frame signal indicating one frame;
an edge interval detector configured to calculate and output interval values between the leading edges;
a storage unit configured to update and store an interval value that is output from the edge interval detector only if the interval value is larger than a previous interval value in a frame, and to maintain and output a value updated as the maximum edge interval value of one frame during a subsequent frame in response to the frame signal; and
a loop filter configured to filter the updated maximum edge interval value in response to the frame signal, and to output the filtered value as an edge interval value indicating the rotational frequency of the optical disk.
7. The optical disk player of claim 6, wherein the loop filter comprises:
a subtractor configured to generate an error value by subtracting the filtered value from the updated maximum edge interval value;
a gain adjuster configured to adjust a reflection degree of the error value and to output an adjustment value; and
a low pass filter configure to low-pass-filter the adjustment value in response to the frame signal and to output the low-pass-filtered value.
8. The optical disk player of claim 7, wherein the low pass filter is configured to output a value, which begins from a predetermined initial value and is increased or decreased by a predetermined value according to the error value, as the low-pass-filtered value.
9. The optical disk player of claim 2, wherein the latch pointer signal has a time period corresponding to a value obtained by dividing the edge interval value by a constant.
10. The optical disk player of claim 2, wherein the latch pointer signal is activated a constant time interval after activation of the edge signal.
11. A BCA data decoding method in an optical disk player, comprising:
generating a radio frequency (RF) signal from information stored on an optical disk;
generating a defect signal from the RF signal;
generating an edge interval value indicating a rotational frequency of the optical disk by checking leading edges of the defect signal;
generating a latch pointer signal having a constant period from the edge interval value; and
generating burst cutting area (BCA) data by decoding the defect signal using the latch pointer signal.
12. The method of claim 11, further comprising:
detecting edge signals indicating the leading edges,
wherein the edge interval value indicating the rotational frequency of the optical disk is updated for a respective frame and a location of the latch pointer signal is compensated when an edge signal is active.
13. The method of claim 11, wherein the rotational frequency of the optical disk is a rotational frequency of an optical disk when the optical disk operates in a constant linear velocity (CLV) mode.
14. The method of claim 11, wherein the edge interval value indicating the rotational frequency of the optical disk is the maximum edge interval value among interval values between the leading edges in one frame.
15. The method of claim 11, wherein the edge interval value indicating the rotational frequency of the optical disk is the minimum edge interval value among interval values between the leading edges in one frame.
16. The method of claim 12, wherein the generation of the edge interval value indicating the rotational frequency comprises:
counting the leading edges and generating a frame signal indicating one frame;
calculating and outputting interval values between the leading edges;
updating and storing a corresponding interval value only if the interval value is larger than a previous interval value in a frame;
maintaining and outputting a value updated as the maximum edge interval value of one frame during a subsequent frame in response to the frame signal; and
filtering the updated maximum edge interval value in response to the frame signal and outputting the filtered value as an edge interval value indicating the rotational frequency of the optical disk.
17. The method of claim 16, wherein the filtering of the updated maximum edge interval value comprises:
generating an error value by subtracting the filtered value from the updated maximum edge interval value;
adjusting a reflection degree of the error value and outputting an adjustment value; and
low-pass-filtering the adjustment value in response to the frame signal and outputting the low-pass-filtered value.
18. The method of claim 17, wherein the low-pass-filtered value begins from a predetermined initial value and is increased or decreased by a predetermined value according to the error value.
19. The method of claim 12, wherein the latch pointer signal has a time period corresponding to a value obtained by dividing the edge interval value by a constant.
20. The method of claim 12, wherein the latch pointer signal is activated a constant time interval after the edge signal is activated.
21. An optical disk player comprising:
a disk spinning system that is configured to spin an optical disk at a constant linear velocity; and
a burst cutting area data decoding system that is configured to decode data in a burst cutting area of the optical disk while the optical disk is spinning at the constant linear velocity.
22. The optical disk player of claim 21 wherein the burst cutting area data decoding system is configured to decode data in the burst cutting area of the optical disk while the optical disk is spinning at the constant linear velocity by determining a rotational frequency of the optical disk while reading the data in the burst cutting area and using the rotational frequency that was determined to decode the data in the burst cutting area that was read.
23. A burst cutting area data decoding method for an optical disk player comprising:
decoding data in a burst cutting area of the optical disk while the optical disk is spinning at the constant linear velocity.
24. The method of claim 23 wherein decoding data in a burst cutting area of the optical disk while the optical disk is spinning at the constant linear velocity comprises:
determining a rotational frequency of the optical disk while reading the data in the burst cutting area; and
using the rotational frequency that was determined to decode the data in the burst cutting area that was read.