1. A shielding for a magnetic resonance tomography (MRT) device, in the form of a shell of a cylinder, for arrangement radially between a radially outer gradient coil system for generating a magnetic field gradient in an examination space of the MRT device, and a radially inner RF coil system for sending, receiving, or sending and receiving RF signals into the examination space and from the examination space, the shielding comprising:
strips that are arranged on a shielding surface, are electrically conductive and are separated from one another by slits,
wherein the strips comprise respectively angled, rounded, or angled and rounded profile segments to create a two-dimensional pattern of shielding rings on the shielding surface.
2. The shielding of claim 1, wherein the strips have an at least approximately uniform strip width.
3. The shielding of claim 1, wherein the shielding rings are respectively interrupted in profile at at least one point.
4. The shielding of claim 1, wherein the shielding rings are arranged at least in a subset of segments as adjoining one another to form shared ring profile segments.
5. The shielding of claim 1, wherein the shielding rings are arranged on a two-dimensional grid on the shielding surface.
6. The shielding of claim 1, further comprising electrically conductive patches on the shielding surface that are arranged respectively within the shielding rings.
7. The shielding of claim 1, further comprising a further shielding surface, on which further electrically conductive strips, patches, or strips and patches that are separated from one another by slits are arranged.
8. The shielding of claim 2, wherein the shielding rings are respectively interrupted in profile at at least one point.
9. The shielding of claim 8, wherein the shielding rings are arranged at least in a subset of segments as adjoining one another to form shared ring profile segments.
10. The shielding of claim 9, wherein the shielding rings are arranged on a two-dimensional grid on the shielding surface.
11. The shielding of claim 10, further comprising electrically conductive patches on the shielding surface that are arranged respectively within the shielding rings.
12. A magnetic resonance tomography (MRT) device comprising:
a radially outer gradient coil system for generating a magnetic field gradient in an examination space of the MRT device,
a radially inner RF coil system for sending, receiving, or sending and receiving RF signals into the examination space and from the examination space,
a shielding in the form of a shell of a cylinder, for arrangement radially between the outer gradient coil system and the inner RF coil system, the shielding comprising strips that are arranged on a shielding surface, are electrically conductive and are separated from one another by slits, wherein the strips comprise respectively angled, rounded, or angled and rounded profile segments to create a two-dimensional pattern of shielding rings on the shielding surface.
13. The MRT device of claim 12, wherein the strips have an at least approximately uniform strip width.
14. The MRT device of claim 12, wherein the shielding rings are respectively interrupted in profile at at least one point.
15. The MRT device of claim 12, wherein the shielding rings are arranged at least in a subset of segments as adjoining one another to form shared ring profile segments.
16. The MRT device of claim 12, wherein the shielding rings are arranged on a two-dimensional grid on the shielding surface.
17. The MRT device of claim 12, wherein the shielding further comprises electrically conductive patches on the shielding surface that are arranged respectively within one of the shielding rings.
18. The MRT device of claim 12, wherein the shielding further comprises a further shielding surface, on which further electrically conductive strips, patches, or strips and patches that are separated from one another by slits are arranged.
19. The MRT device of claim 13, wherein the shielding rings are respectively interrupted in profile at at least one point.
20. The MRT device claim 19, wherein the shielding rings are arranged at least in a subset of segments as adjoining one another to form shared ring profile segments.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor device, comprising:
a word line;
a charge storage region located above the word line;
an active layer located above the charge storage region;
a patterned etch stop layer located above a first portion of the active layer; and
bit lines located over a portion of the etch stop layer and over second portions of the active layer.
2. The device of claim 1, wherein:
the charge storage region is located on the word line;
the active layer is located on the charge storage region;
the patterned etch stop layer is located on the first portion of the active layer but not on second portions of the active layer;
the first portion of the active layer comprises a semiconductor transistor channel region of a first conductivity type;
the second portions of the active layer comprise semiconductor transistor source and drain regions of a second conductivity type;
an edge portion of a first bit line is located on the etch stop layer and a middle portion of the first bit line is located on the source region; and
an edge portion of a second bit line is located on the etch stop layer and a middle portion of the second bit line is located on the drain region.
3. The device of claim 2, wherein:
the word line comprises a heavily doped polysilicon layer over a metal silicide layer;
the charge storage region comprises a dielectric isolated floating gate, an insulating layer containing conductive nanocrystals or a composite dielectric film comprising a tunneling layer, a charge storage layer and a blocking oxide;
the active layer comprises a polysilicon layer;
the etch stop layer comprises a material which can be selectively etched compared to polysilicon;
the source and drain regions comprise heavily doped polysilicon regions; and
the bit lines comprise a first polysilicon layer contacting the source and drain regions and a metal silicide layer contacting the first polysilicon layer.
4. The device of claim 3, wherein:
the charge storage region comprises the composite dielectric film comprising an oxide tunneling layer, a nitride charge storage layer, and the blocking oxide;
the etch stop layer comprises a silicon oxide, silicon nitride or a silicon oxynitride layer;
the bit lines comprise the first polysilicon layer contacting the source and drain regions, a titanium silicide layer contacting the first polysilicon layer, a titanium nitride layer contacting the titanium silicide layer, and a second polysilicon layer contacting the titanium silicide layer; and
a portion of the bit lines, a portion of the word line, a portion of the charge storage region, the source, the drain and the channel comprise a first inverted staggered thin film transistor.
5. The device of claim 4, further comprising:
a plurality of word lines located at a first height and extending in a first direction;
a plurality of bit lines located at a second height above the first height and extending in a second direction different from the first direction, wherein the charge storage region and the active layer are located between the plurality of word lines and the plurality of bit lines; and
a plurality of the first inverted staggered thin film transistors are located at intersections of the word lines and the bit lines in a first device level.
6. The device of claim 5, further comprising at least one second device level monolithically formed above the first device level, wherein the at least one second device level comprises a plurality of second inverted staggered thin film transistors.
7. A monolithic, three dimensional array of thin film transistors, comprising:
a first device level comprising a plurality of first inverted staggered thin film transistors; and
a second device level monolithically formed over the first device level, the second device level comprising a plurality of second thin film transistors; and
wherein the first inverted staggered thin film transistors comprise a first etch stop layer located over transistor channel regions.
8. The array of claim 7, further comprising:
a plurality of first gate lines at a first height and extending in a first direction;
a first planarized insulating fill layer located between the first gate lines;
a first gate insulating layer located on the first gate lines and on the first insulating fill layer;
a first active layer located on the first gate insulating layer;
a patterned etch stop layer located on channel regions in the first active layer;
a plurality of first source and drain lines located on source and drain regions in the first active layer and on portions of the patterned etch stop layer, the first source and drain lines extending in a second direction different from the first direction;
a second active layer located on the first source and drain lines;
a second gate insulating layer located on the second active layer;
a plurality of second gate lines located on the second gate insulating layer, the second gate lines extending in the first direction.
9. The array of claim 8, wherein:
the first and the second transistors share the first source and drain lines;
the first device level comprises the first gate lines and the first source and drain lines; and
the second device level comprises the second gate lines and the first source and drain lines.
10. The array of claim 9, wherein:
the channel, source and drain regions of each first transistor are located in a portion of the first active layer;
a gate insulating region of each first transistor is located in a portion of the first gate insulating layer;
a gate electrode of each first transistor is located in a portion of one of the first gate lines;
channel, source and drain regions of each second transistor are located in a portion of the second active layer;
a gate insulating region of each second transistor is located in a portion of the second gate insulating layer;
a gate electrode of each second transistor is located in a portion of one of the second gate lines; and
each second transistor comprises a top gate staggered thin film transistor.
11. The array of claim 10, further comprising:
a third gate insulating layer located on the second gate lines;
a third active layer located on the third gate insulating layer;
a second patterned etch stop layer located on the third active layer;
a plurality of the second source and drain lines located on the third active layer and on the second patterned etch stop layer, wherein the plurality of second source and drain lines extend in a second direction different from the first direction; and
a plurality of third inverted staggered thin film transistors.
12. The array of claim 11, wherein:
the second and the third transistors share the second gate lines;
channel, source and drain regions of each third transistor are located in a portion of the third active layer;
a gate insulating region of each third transistor is located in a portion of the third gate insulating layer;
a gate electrode of each third transistor is located in a portion of one of the second gate lines; and
source and drain lines of each third transistor comprise the second source and drain lines.
13. The array of claim 12, wherein:
the first gate lines comprise a heavily doped polysilicon layer over a metal silicide layer;
the second gate lines comprise a metal suicide layer located between two heavily doped polysilicon layers;
the first, second and third gate insulating layers comprise a portion of a charge storage region selected from a group consisting of: a dielectric isolated floating gate, an insulating layer containing conductive nanocrystals, and a composite dielectric film comprising a tunneling layer, a charge storage layer and a blocking oxide;
the first, second and third active layers comprise a polysilicon layer;
the etch stop layer comprises a material which can be selectively etched compared to polysilicon;
the source and drain regions comprise heavily doped polysilicon regions; and
the first and second source and drain lines comprise at least a first polysilicon layer.
14. The array of claim 13, wherein:
the charge storage regions comprise the composite dielectric film comprising an oxide tunneling layer, a nitride charge storage layer, and the blocking oxide;
the etch stop layer comprises a silicon oxide, silicon nitride or a silicon oxynitride layer; and
the first and the second source and drain lines comprise the first polysilicon layer contacting the source and drain regions of the first transistors, a titanium silicide layer contacting the first polysilicon layer, a titanium nitride layer contacting the titanium silicide layer and a second polysilicon layer contacting the titanium silicide layer.
15. The array of claim 12, wherein the first and second transistors comprise metal oxide semiconductor transistors of a first conductivity type and the third transistors comprise metal oxide semiconductor transistors of a second conductivity type.
16. An array of inverted staggered thin film transistors, comprising:
a plurality of gate lines;
a planarized insulating fill layer located between the gate lines;
a gate insulating layer located on the fill layer and on exposed portions of the gate lines;
an active layer located on the gate insulating layer;
a patterned etch stop layer located on first portions of the active layer; and
a plurality of source and drain lines located on second portions of the active layer and on portions of the patterned etch stop layer.
17. The array of claim 16, wherein:
the gate lines comprise a heavily doped polysilicon layer over a metal silicide layer;
the insulating fill layer comprises a chemically mechanically polished silicon dioxide layer;
the gate insulating layer comprises portion of a charge storage region selected from a group consisting of: a dielectric isolated floating gate, an insulating layer containing conductive nanocrystals, and a composite dielectric film comprising a tunneling layer, a charge storage layer and a blocking oxide;
the active layer comprises a polysilicon layer;
the first portions of the active layer comprise lightly doped or intrinsic channel regions of a first conductivity type;
the second portions of the active layer comprise heavily doped source and drain regions of a second conductivity type;
the etch stop layer comprises a material which can be selectively etched compared to polysilicon; and
the source and drain lines comprise at least a first polysilicon layer.
18. The array of claim 17, wherein:
the charge storage regions comprise the composite dielectric film comprising an oxide tunneling layer, a nitride charge storage layer, and the blocking oxide;
the etch stop layer comprises a silicon oxide, silicon nitride or a silicon oxynitride layer; and
the source and drain lines comprise the first polysilicon layer contacting the source and drain regions of the transistors, a titanium silicide layer contacting the first polysilicon layer; a titanium nitride layer contacting the titanium silicide layer and a second polysilicon layer contacting the titanium silicide layer.
19. A method of making semiconductor device, comprising:
forming a first gate line layer;
patterning the first gate line layer to form a plurality of first gate lines;
forming a first insulating fill layer over and between the first gate lines;
planarizing the first fill layer with a top surface of the first gate lines;
forming a first gate insulating layer over the first gate lines and the first fill layer;
forming a first active layer over the first gate insulating layer;
forming a first etch stop layer over the first active layer;
selectively patterning the first etch stop layer such that first portions of the first active layer are covered by the etch stop layer and second portions of the first active layer are exposed;
forming a first sourcedrain line film over the first patterned etch stop layer and the exposed second portions of the first active layer; and
selectively patterning the first sourcedrain line film to form first source and drain lines and to expose portions of the first patterned etch stop layer between the first source and drain lines.
20. The method of claim 19, wherein the step of selectively patterning the first sourcedrain line film comprises patterning the sourcedrain line film such that a portion of the first source and the drain lines are located on the etch stop layer.
21. The method of claim 20, wherein the step of forming the first sourcedrain line film comprises:
forming a first heavily doped amorphous silicon layer;
forming a titanium layer on the amorphous silicon layer;
forming a titanium nitride layer on the titanium layer;
annealing the amorphous silicon layer and the titanium layer to convert the amorphous silicon layer to a polysilicon layer, to react the titanium layer with the underlying amorphous silicon layer to form a titanium silicide layer and to outdiffuse dopants from the amorphous silicon layer into the first active layer to form source and drain regions in the first active layer; and
depositing a second heavily doped polysilicon layer on the titanium nitride layer.
22. The method of claim 21, further comprising:
forming a second insulating fill layer over and between the first source and drain lines;
planarizing the second fill layer with a top surface of the first source and drain lines;
depositing a second active layer over the first source and drain lines and over the second fill layer;
annealing the second active layer to outdiffuse dopants from the second heavily doped polysilicon layer into the second active layer to form source and drain regions in the second active layer;
forming a second gate insulating layer over the second active layer; and
forming second gate lines over the second gate insulating layer.
23. The method of claim 22, further comprising:
forming a third insulating fill layer over and between the second gate lines;
planarizing the third fill layer with a top surface of the second gate lines;
forming a third gate insulating layer over the second gate lines and the third fill layer;
forming a third active layer over the third gate insulating layer;
forming a second etch stop layer over the third active layer;
selectively patterning the second etch stop layer such that first portions of the third active layer are covered by the second etch stop layer and second portions of the third active layer are exposed;
forming a second sourcedrain line film over the second patterned etch stop layer and exposed second portions of the third active layer; and
selectively patterning the second sourcedrain line film to form second source and drain lines and to expose portions of the second patterned etch stop layer between the second source and drain lines.
24. The array of claim 19, wherein:
the first gate lines comprise a heavily doped polysilicon layer over a metal silicide layer;
the first insulating fill layer comprises a chemically mechanically polished silicon dioxide layer;
the first gate insulating layer comprises portion of a charge storage region selected from a group consisting of: a dielectric isolated floating gate, an insulating layer containing conductive nanocrystals, and a composite dielectric film comprising a tunneling layer, a charge storage layer and a blocking oxide;
the first active layer comprises a polysilicon layer;
the etch stop layer comprises a material which can be selectively etched compared to polysilicon; and
the first source and drain lines comprise at least a first polysilicon layer.
25. The method of claim 24, wherein:
the first charge storage region comprises the composite dielectric film comprising an oxide tunneling layer, a nitride charge storage layer, and the blocking oxide; and
the first etch stop layer comprises a silicon oxide, silicon nitride or a silicon oxynitride layer.
26. The method of claim 19, wherein:
selectively patterning the etch stop layer comprises selectively etching the etch stop layer using an etching gas or liquid which preferentially etches a material of the etch stop layer compared to a material of the active layer; and
selectively patterning the first sourcedrain line film comprises selectively etching the first sourcedrain line film using an etching gas or liquid which preferentially etches a material of the first sourcedrain line film compared to the material of the etch stop layer.