What is claimed is:
1. An apparatus for detecting a data transmission rate transmitted through a serial bus, the apparatus comprising:
a data transmission rate detecting unit for detecting a data transmission rate of bit stream data transmitted through a predetermined transmission line;
a sampler for sampling a data transmission rate detected by the data transmission rate detecting unit at a predetermined period;
a low-pass filter for low-pass filtering a value sampled by the sampler to produce a low-pass filtered value;
an error detecting unit for detecting an error value in the data transmission rate of the transmitted bit stream data using the value sampled by the sampler and the low-pass filtered value;
a comparing unit for comparing the error value detected by the error detecting unit with a reference error level; and
an estimated data transmission rate output unit for outputting an estimated data transmission rate based on the low-pass filtered value when the error value is smaller than the reference error level.
2. The apparatus for detecting a data transmission rate according to claim 1, wherein the error detecting unit is formed to detect an error value of one isochronous period, the comparing unit is formed to compare the error value of the one isochronous period with the reference error level, and the estimated data transmission rate output unit is formed to output the estimated data transmission rate of the one isochronous period, in a case where the serial bus is an IEEE 1394 bus.
3. The apparatus for detecting a data transmission rate according to claim 2, wherein the error detecting unit is formed to calculate a low-pass filtered value of the one isochronous period from the low-pass filtered value, to calculate a sampled value of the one isochronous period from the sampled value, to divide an absolute difference between the low-pass filtered value of the one isochronous period and the sampled value of the one isochronous period by the low-pass filtered value of the one isochronous period, and to detect an error of the one isochronous period.
4. The apparatus for detecting a data transmission rate according to claim 2, wherein the comparing unit sets one error level selected from a plurality of error levels by a user as the reference error level.
5. The apparatus for detecting a data transmission rate according to claim 2, wherein the error detecting unit is formed to calculate a low-pass filtered value of the one isochronous period from the low-pass filtered value, to calculate a sampled value of the one isochronous period from the sampled value, to divide an absolute difference between the low-pass filtered value of the one isochronous period and the sampled value of the one isochronous period by the low-pass filtered value of the one isochronous period, and to detect an error value of the one isochronous period; and
wherein the comparing unit sets a value obtained when one error level selected by a user from a plurality of error levels is multiplied by the sampled value of the one isochronous period, as the reference error level, and is formed to compare the error value of the one isochronous period with the reference error level.
6. The apparatus for detecting a data transmission rate according to claim 2, wherein the estimated data transmission rate output unit calculates a low-pass filtered value of the one isochronous period from the low-pass filtered value and outputs the low-pass filtered value of the one isochronous period as the estimated data transmission rate.
7. The apparatus for detecting a data transmission rate according to claim 2, wherein the low-pass filter is an infinite impulse response (IIR) low-pass filter.
8. The apparatus for detecting a data transmission rate according to claim 1, wherein the predetermined transmission line is a line between an external inputoutput interface unit for interfacing with an MPEG transport stream (TS) demultiplexer and an audiovideo interface unit.
9. The apparatus for detecting a data transmission rate according to claim 1, wherein the apparatus detects the data transmission rate in a word unit, and a predetermined sampling frequency is set to 125 Hz.
10. An apparatus for detecting a data transmission rate through a serial bus after a bandwidth for the serial bus is allocated to a system, the apparatus comprising:
a data transmission rate detecting unit for detecting a data transmission rate of bit stream data transmitted through a predetermined transmission line;
a sampler for sampling a data transmission rate detected by the data transmission rate detecting unit at a predetermined period;
a low-pass filter for low-pass filtering a value sampled by the sampler;
an error detecting unit for detecting an error value in the data transmission rate of the transmitted bit stream data using the value sampled by the sampler and a low-pass filtered value;
a first comparing unit for comparing the error value detected by the error detecting unit with a reference error level;
an estimated data transmission rate output unit for outputting an estimated data transmission rate based on the low-pass filtered value when the error value is smaller than the reference error level; and
a second comparing unit for comparing the estimated data transmission rate with an upper bound and a lower bound to notify whether the estimated data transmission rate output from the estimated data transmission rate output unit exists between the upper bound and the lower bound set by a user according to the allocated bandwidth and to determine whether the estimated data transmission rate is output.
11. The apparatus for detecting a data transmission rate according to claim 10, wherein the second comparing unit generates an interrupt for notifying whether the estimated data transmission rate output from the estimated data transmission rate output unit exists between the upper bound and the lower bound and an output control signal to the estimated data transmission rate output unit so as to output the estimated data transmission rate, in a case where the estimated data transmission rate does not exist between the upper bound and the lower bound.
12. The apparatus for detecting a data transmission rate according to claim 10, wherein the error detecting unit is formed to detect an error value of one isochronous period, the first comparing unit is formed to compare the error value of the one isochronous period with the reference error level, and the estimated data transmission rate output unit is formed to output an estimated data transmission rate of the one isochronous period, in a case where the serial bus is an IEEE 1394 bus.
13. The apparatus for detecting a data transmission rate according to claim 10, wherein the predetermined transmission line is a line between an external inputoutput interface unit for interfacing with an MPEG transport stream (TS) demultiplexer and an audiovideo interface unit.
14. A method for detecting a data transmission rate through a serial bus, the method comprising the steps of:
(a) detecting a data transmission rate of bit stream data transmitted through a predetermined transmission line;
(b) detecting an error in the data transmission rate at a first predetermined period using the detected data transmission rate;
(c) comparing the error with a reference error level;
(d) checking present operation mode when the error is smaller than the reference error level;
(e) outputting an estimated data transmission rate for the first predetermined period using the data transmission rate when the present operation mode is a transmitreceive average mode; and
(f) outputting the estimated data transmission rate for the first predetermined period in a case where the estimated data transmission rate for the first predetermined period does not exist between a predetermined upper bound and a predetermined lower bound when the present operation mode is a transmitreceive tracking mode.
15. The method for detecting a data transmission rate according to claim 14, wherein the step (b) comprises the steps of:
(b1) sampling the detected data transmission rate at a first predetermined frequency;
(b2) filtering a sampled value in the step (b1) by using low-pass filtering; and
(b3) detecting the error in the data transmission rate of the bit stream data using the sampled value and a low-pass filtered value in the step (b2).
16. The method for detecting a data transmission rate according to claim 15, wherein the reference error level in the step (c) is one error level selected from a plurality of error levels by a user, or a value resulting from performing a predetermined operation on the one error level and the sampled value.
17. The method for detecting a data transmission rate according to claim 15, wherein the step(a) is performed in a word unit, the first predetermined period is one isochronous period, and the first predetermined frequency is 125 Hz, in a case where the serial bus is an IEEE 1394 bus.
18. The method for detecting a data transmission rate according to claim 15, wherein the low-pass filtered value of the first predetermined period detected using the low-pass filtered value in the step (b2) is output as the estimated data transmission rate in the steps (e) and (f).
19. The method for detecting a data transmission rate according to claim 14, wherein the predetermined upper bound and the predetermined lower bound in the step (f) are determined on the basis of the estimated data transmission rate output in the step (e), and the step (f) comprises the step of notifying whether the estimated data transmission rate exists between the predetermined upper bound and the predetermined lower bound.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A battery pack, comprising:
a battery cell having a terminal;
a protection circuit module having a through-hole at a region corresponding to the terminal; and
a case coupled to the battery cell and covering the protection circuit module, wherein the protection circuit module includes at least one first mechanical mating feature adjacent the through-hole.
2. The battery pack as claimed in claim 1, further comprising:
a plurality of first mechanical mating features adjacent respective sides of the through-hole.
3. The battery pack as claimed in claim 1, wherein the case has a second mechanical mating feature complementary to the first mechanical mating feature at a location corresponding to the protrusion.
4. The battery pack as claimed in claim 1, wherein the first mechanical mating feature is in a width direction of the protection circuit module.
5. The battery pack as claimed in claim 1, wherein the first mechanical mating feature includes a first wire pattern to carry a charge current or a discharge current.
6. The battery pack as claimed in claim 5, wherein the first wire pattern has substantially a same width and substantially a same thickness as a second wire pattern located in a region that does not include the first mechanical mating feature.
7. The battery pack as claimed in claim 5, wherein:
the protection circuit module has opposing top and bottom surfaces, and
the first wire pattern is on at least one of the top or bottom surface.
8. The battery pack as claimed in claim 1, wherein the first mechanical mating feature is in a thickness direction of the protection circuit module.
9. The battery pack as claimed in claim 8, wherein the first mechanical mating feature includes:
a first wire pattern to carry a charge current or a discharge current; and
a second wire pattern connected to the first wire pattern in parallel.
10. The battery pack as claimed in claim 9, wherein:
the protection circuit module has opposing top and bottom surfaces, and
the first and second wire patterns are formed on at least one of the top or bottom surfaces.
11. The battery pack as claimed in claim 8, wherein the first mechanical mating feature includes the first wire pattern to carry a charge current or a discharge current.
12. The battery pack as claimed in claim 11, wherein the first wire pattern has a width and a thickness different from a width and a thickness of a second wire pattern located in a region which does not include the first mechanical mating feature.
13. The battery pack as claimed in claim 12, wherein:
the width of the first wire pattern is less than the width of the second wire pattern, and
the thickness of the first wire pattern is greater than the width of the second wire pattern.
14. The battery pack as claimed in claim 13, wherein:
the protection circuit module has opposing top and bottom surfaces, and
the first wire pattern is on at least one of the top or bottom surfaces.
15. The battery pack as claimed in claim 1, further comprising:
a conductive tab to electrically connect the battery cell to the protection circuit module at a region corresponding to the through-hole of the protection circuit module.
16. The battery pack as claimed in claim 1, further comprising:
an insulation holder between the battery cell and protection circuit module, wherein a width of the first mechanical mating feature of the protection circuit module is greater than a width of the insulation holder.
17. A battery pack, comprising:
a battery cell including a terminal; and
a substrate including a conductive pattern adjacent a hole,
wherein the hole is aligned with the terminal and wherein the at least one conductive pattern has a first section with an edge spaced a first distance from a first axis passing through the hole and a second section with an edge spaced a second distance from the first axis, the first distance different from the second distance.
18. The battery pack as claimed in claim 17, wherein the first and second sections have substantially equal widths.
19. The battery pack as claimed in claim 17, wherein the hole and second section are aligned along a second axis substantially perpendicular to the first axis.
20. The battery pack as claimed in claim 17, the first and second sections carry charge or discharge current.