1. A semiconductor storage device, comprising:
a plurality of flash memory chips, comprising a plurality of physical blocks, each of which is a unit of erasing data, and comprises a plurality of physical pages, each of which is a unit of reading or writing data; and
a flash memory controller configured to control a reading or writing operation to the plurality of flash memory chips,
wherein the flash memory controller is configured to:
receive write data;
compress the write data to compressed data;
store the compressed data into at least one physical page of the plurality of flash memory chips when a number of physical pages required to store the compressed data is smaller than a number of physical pages required to store the write data;
manage a logical address space which is an access target of an access request source by dividing the logical address space into a plurality of logical pages, and manage each of the pages in association with the physical pages which belong to an of the physical blocks, and when any of the logical pages is designated in response to a write request from the access request source:
select one, two or more of the physical pages as physical pages which correspond to the designated logical pages; and
store compressed write data on the selected physical pages, form a virtual physical page for storing the compressed write data as data when the compressed write data is virtually decompressed, and change the corresponding relationship between the designated logical page and the one, two or more of the physical pages of the physical block corresponding to the logical page into a corresponding relationship between the designated logical page and the virtual physical pages;
when a logical page, which is the same as the designated logical page, is designated in response to a subsequent access request, process the virtual physical page as an access destination;
accumulate write data which is added to each of the write requests each time a write request is received from the access request source, and batch-compress a plurality of the accumulated write data;
when a compression effect of the compressed write data is greater than a designated value, assuming said condition is fulfilled, store the compressed write data on the selected physical page; and
when the compression effect of the compressed write data is smaller than a designated value, assuming said condition is fulfilled, store the write data added to each of the write requests on the selected physical page.
2. The semiconductor storage device according to claim 1,
wherein each of the physical blocks is divided into a base area configured to store new write data among the write data related to a write request and into an update area configured to store an update data which is configured to update the data stored in the base area, and a plurality of physical pages are respectively assigned to the base area and the update area,
wherein the flash memory controller is configured to:
manage a logical address space which is an access target;
divide the logical address space into a plurality of logical groups, wherein each of the logical groups is associated with the base area of each of the physical blocks;
receive a write request designating a logical address of the logical address space;
specify a logical group including the designated logical address;
select a physical block within the base area for storing the compressed write data;
store the compressed write data into a physical page in the selected physical block;
form a virtual page assigned to the physical page which stores the compressed data, for managing the compressed write data as data when the compressed write data is virtually decompressed;
change the corresponding relationship between the specified logical group and the physical page into a corresponding relationship between the specified logical group and the virtual page; and
process the physical page which is assigned to the virtual page as an access destination when the specified logical group, is designated by a subsequent access request.
3. The semiconductor storage device according to claim 1,
wherein each of the physical blocks is divided into a base area which is a storage destination of new write data among write data applied to the access request and an update area which is a storage destination of update data, and a plurality of physical pages are respectively assigned to the base area and the update area,
wherein when, as a result of the write data compression, the physical pages serving as write targets among the physical pages which belong to the selected physical block are reduced, the flash memory controller is configured to:
reduce a number of physical pages assigned to the base area belonging to the selected physical block; and
increase a number of physical pages assigned to the update area belonging to the selected physical block.
4. The semiconductor storage device according to claim 1,
wherein each of the physical blocks is divided into a base area which is a storage destination of new write data among write data applied to the access request and an update area which is a storage destination of update data, and a plurality of physical pages are respectively assigned to the base area and the update area,
wherein the flash memory controller is configured to:
compare, among the write data, the data size of the write data before the compression with the data size of the write data after the compression;
write the write data after the compression to the base area when the data size of the write data after the compression is smaller than the data size of the write data before the compression by at least size of the physical page; and
write the write data before the compression to the base area when the data size of the write data after the compression is not smaller than the data size of the write data before the compression by at least size of the physical page.
5. The semiconductor storage device according to claim 1,
wherein each of the physical blocks is divided into a base area which is a storage destination of new write data among write data applied to the access request and into an update area which is a storage destination of update data, and a plurality of physical pages are respectively assigned to the base area and the update area,
wherein the flash memory controller is configured to, when the data stored on the physical page of the base area belonging to any of the physical blocks is updated in response to the write request as update source data;
create update data from the update source data and the write data applied to the write request;
write the created update data to the update area which belongs to the same physical block as the update source data, and creates update area management information which associates an update source address indicating an access destination of the update source data with an update area address indicating a write destination of the update data, and if the access request is a read request and the update source data is designated in response to the read request;
search for the update area management information;
acquire the update area address; and
read the update data from the update area according to the acquired update area address.
6. The semiconductor storage device according to claim 1,
wherein each of the physical blocks is divided into a base area which is a storage destination of new write data among write data applied to the access request and an update area which is a storage destination of update data, and a plurality of physical pages are respectively assigned to the base area and the update area,
wherein the flash memory controller is configured to, when unwritten physical pages of the update area belonging to any of the physical blocks are exhausted, manage the physical block as a reclamation target physical block, and read data of the base area belonging to the reclamation target physical block and update data of the update area belonging to the reclamation target physical block respectively on a data buffer; and
when the read frequency of data read on the data buffer is smaller than a designated value, assuming said condition is fulfilled, compress the data read on the data buffer, erase data in the reclamation target physical block from which data was read onto the data buffer, and write the data compressed on the data buffer to the reclamation target physical block from which the data was erased or to the base area of another physical block which differs from the reclamation target physical block.
7. The semiconductor storage device according to claim 1,
wherein each of the physical blocks is divided into a base area which is a storage destination of new write data among write data applied to the access request and an update area which is a storage destination of update data, and a plurality of physical pages are respectively assigned to the base area and the update area,
wherein the flash memory controller is configured to:
when all the data stored in any of the physical blocks has not been an access target for a definite period since being stored, manage, among the physical blocks, a physical block in which data has not been an access target for a definite period since being stored as a refresh target physical block, and read data in the refresh target physical block on a data buffer and
when the read frequency of data read on the data buffer is smaller than a designated value, assuming the above condition is fulfilled, compress the data read on the data buffer, erase data in the refresh target physical block from which data was read onto the data buffer, and write the data compressed on the data buffer to the refresh target physical block from which the data was erased or to the base area of another physical block which differs from the refresh target physical block.
8. The semiconductor storage device according to claim 1,
wherein the flash memory controller is configured to, when unwritten physical pages belonging to any of the physical blocks are exhausted:
manage the physical block as a reclamation target physical block;
read data in the reclamation target physical block onto a data buffer;
determine a read frequency level of data read on the data buffer;
batch-compress data with a low read frequency among the data read on the data buffer on the basis of the determination result;
erase data in the reclamation target physical block from which data was read onto the data buffer; and
write the data compressed on the data buffer to the reclamation target physical block from which the data was erased or to the physical pages of another physical block which differs from the reclamation target physical block; and
when all the data stored on a physical page which belongs to any of the physical blocks has not been an access target for a definite period since being stored:
manage the physical block as a refresh target physical block;
read data in the refresh target physical block onto the data buffer;
determine a read frequency level of data read on the data buffer;
batch-compress data with a low read frequency among the data read on the data buffer on the basis of the determination result, erases data in the refresh target physical block from which data was read onto the data buffer; and
write the data compressed on the data buffer to the refresh target physical block from which the data was erased or to the physical pages of another physical block which differs from the reclamation target physical block.
9. A data control method for a semiconductor storage device, the method comprising:
controlling, by a flash memory controller, a reading or writing operation to a plurality of flash memory chips, comprising a plurality of physical blocks, each of which is a unit of erasing data, and comprises a plurality of physical pages, each of which is a unit of reading or writing data,
wherein each of the physical blocks is divided into a base area configured to store new write data among write data and into an update area configured to update data stored in the base area, and a plurality of physical pages are respectively assigned to the base area and the update area;
receiving, by the flash memory controller, write data;
compressing, by the flash memory controller, write data to compress data; and
storing, by the flash memory controller, the compressed data into at least one physical page of the plurality of flash memory chips when a number of physical pages required to store the compressed data is smaller than a number of physical pages required to store the write data;
managing a logical address space which is an access target of an access request source by dividing the logical address space into a plurality of logical pages, and managing each of the logical pages in association with the physical pages which belong to any of the physical blocks, and when any of the logical pages is designated in response to a write request from the access request source:
selecting one, two or more of the physical pages as physical pages which correspond to the designated logical pages; and
storing compressed write data on the selected physical pages, forming a virtual physical page for storing the compressed write data as data when the compressed write data is virtually decompressed, and changing the corresponding relationship between the designated logical page and the one, two or more of the physical pages of the physical block corresponding to the logical page into a corresponding relationship between the designated logical page and the virtual physical pages;
when a logical page, which is the same as the designated logical page, is designated in response to a subsequent access request, processing the virtual physical page as an access destination;
accumulating write data which is added to each of the write requests each time a write request is received from the access request source, and batch-compressing a plurality of the accumulated write data;
when a compression effect of the compressed write data is greater than a designated value, assuming said condition is fulfilled, storing the compressed write data on the selected physical page; and
when the compression effect of the compressed write data is smaller than a designated value, assuming said condition is fulfilled, storing the write data added to each of the write requests on the selected physical page.
10. The data control method for a semiconductor storage device according to claim 9, further comprising:
managing, by the flash memory controller, a logical address space which is an access target group;
dividing, by the flash memory controller, the logical address space into a plurality of logical groups, wherein each of the logical groups is associated with the base area of each of the physical blocks;
receiving a write request designating a logical address of the logical address space;
specifying a logical group including the designated logical address;
selecting a physical block within the base area for storing the compressed write data;
storing the compressed write data into a physical page in the selected base physical block;
forming a virtual page assigned to the physical page which stores the compressed data, for managing the compressed write data as data when the compressed write data is virtually decompressed;
changing the corresponding relationship between the specified logical group and the physical page into a corresponding relationship between the specified logical group and the virtual page; and
when a logical group is designated by a subsequent access request, processing the physical page which is assigned to the virtual page as an access destination.
11. The data control method for a semiconductor storage device according to claim 9, further comprising:
when, as a result of the write data compression, the physical pages serving as write targets among the physical pages which belong to the selected physical block are reduced, reducing, by the flash memory controller, a number of physical pages assigned to the base area belonging to the selected physical block; and
increasing, by the flash memory controller, a number of physical pages assigned to the update area belonging to the selected physical block.
12. The data control method for a semiconductor storage device according to claim 9, further comprising:
comparing, by the flash memory controller, among the write data, the data size of the write data before the compression with the data size of the write data after the compression;
when the data size of the write data after the compression is smaller than the data size of the write data before the compression by at least size of the physical page, writing, by the flash memory controller, the write data after the compression to the base area; and
when the data size of the write data after the compression is not smaller than the data size of the write data before the compression by at least size of the physical page, writing, by the flash memory controller, the write data before the compression to the base area.
13. The data control method for a semiconductor storage device according to claim 9, further comprising:
when the data stored on the physical page of the base area belonging to any of the physical blocks is updated by the write request as update source data:
creating, by the flash memory controller, update data from the update source data and the write data applied to the write request;
writing, by the flash memory controller, the created update data to the update area which belongs to the same physical block as the update source data; and
creating, by the flash memory controller, update area management information which associates an update source address indicating an access destination of the update source data with an update area address indicating a write destination of the update data; and
when the access request is a read request and the update source data is designated in response to the read request:
searching, by the flash memory controller, for the update area management information, acquires the update area address; and
reading, by the flash memory controller, the update data from the update area according to the acquired update area address.
14. A storage system comprising:
a plurality of semiconductor storage devices, and
a storage controller configured to control the plurality of semiconductor storage devices as a RAID group,
wherein each of the plurality of semiconductor storage devices comprises:
a plurality of flash memory chips which comprise a plurality of physical blocks, each of which is a unit of erasing data, and comprises a plurality of physical pages, each of which is a unit of reading or writing data; and
a flash memory controller which is configured to:
control reading or writing operation to the plurality of flash memory chips;
receive write data;
compress the write data to compressed data;
store the compressed data into at least one physical page of the plurality of flash memory chips when a number of a physical page required to store the compressed data is smaller than a number of physical pages required to store the write data;
manage a logical address space which is an access target of an access request source by dividing the logical address space into a plurality of logical pages, and manage each of the logical pages in association with the physical pages which belong to any of the physical blocks, and when any of the logical pages is designated in response to a write request from the access request source:
select one, two or more of the physical pages as physical pages which correspond to the designated logical pages; and
store compressed write data on the selected physical pages, form a virtual physical page for storing the compressed write data as data when the compressed write data is virtually decompressed, and change the corresponding relationship between the designated logical page and the one, two or more of the physical pages of the physical block corresponding to the logical page into a corresponding relationship between the designated logical page and the virtual physical pages;
when a logical page, which is the same as the designated logical page, is designated in response to a subsequent access request, process the virtual physical page as an access destination;
accumulate write data which is added to each of the write requests each time a write request is received from the access request source, and batch-compress a plurality of the accumulated write data;
when a compression effect of the compressed write data is greater than a designated value, assuming said condition is fulfilled, store the compressed write data on the selected physical page; and
when the compression effect of the compressed write data is smaller than a designated value, assuming said condition is fulfilled, store the write data added to each of the write requests on the selected physical page.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power amplifier comprising:
a first amplification path including a power amplification element having one or more power amplification stages, an output impedance modification element, and an output phase shift element being only one inductance, the output impedance modification element coupled between an output of a final stage of the power amplification element and a corresponding intermediate node, the output phase shift element coupled between the corresponding intermediate node and an output node; and
a second amplification path including a power amplification element having one or more power amplification stages, an output impedance modification element, and an output phase shift element being only one capacitance, the output impedance modification element coupled between an output of a final stage of the power amplification element and a corresponding intermediate node, the output phase shift element directly coupled between the corresponding intermediate node and the output node that is common to the first and second amplification paths, the output impedance modification element being a separate structure from the output phase shift element in each amplification path allowing an impedance at each of the intermediate nodes to be substantially the same as an impedance at the output node.
2. The power amplifier of claim 1 wherein the first amplification path further includes an input phase shift element configured to apply a positive phase shift to a radio frequency (RF) input signal.
3. The power amplifier of claim 2 wherein the power amplification element of the first amplification path is configured to receive and amplify the positive phase shifted signal of the first amplification path.
4. The power amplifier of claim 3 wherein the output impedance modification element of the first amplification path is configured to alter an impedance at the output of the final stage of the power amplification element of the first amplification path.
5. The power amplifier of claim 4 wherein the output phase shift element of the first amplification path is configured to apply a negative phase shift to the amplified positive phase shifted signal of the first amplification path.
6. The power amplifier of claim 1 wherein the second amplification path further includes an input phase shift element configured to apply a negative phase shift to the radio frequency (RF) input signal.
7. The power amplifier of claim 6 wherein the power amplification element of the second amplification path is configured to receive and amplify the negative phase shifted signal of the second amplification path.
8. The power amplifier of claim 7 wherein the output impedance modification element of the second amplification path is configured to alter an impedance at the output of the final stage of the power amplification element of the second amplification path.
9. The power amplifier of claim 8 wherein the output phase shift element of the second amplification path is configured to apply a positive phase shift to the amplified negative phase shifted signal of the second amplification path.
10. A portable communication device comprising:
a baseband subsystem configured to convert an input signal into a baseband information signal;
a transceiver configured to receive the baseband information signal and modulate and upconvert the received baseband information signal to provide an upconverted signal;
a power amplifier configured to amplify the upconverted signal and including a plurality of amplification paths in which at least one amplification path is selectively enabled and disabled and at least one other amplification path operates whether the at least one amplification path is enabled or disabled, each amplification path including an amplifier element having one or more amplifier stages, an output impedance modification element, and an output phase shift element being one of an inductance and another output phase shift element being only one capacitance, the output impedance modification element coupled between an output of a final stage of the amplifier element and an intermediate node, the other output phase shift element directly coupled between the intermediate node and an output node that is common to the plurality of amplification paths, the output impedance modification element being a separate structure from the output phase shift element in each amplification path allowing an impedance at each of the intermediate nodes to be substantially the same as an impedance at the output node; and
an antenna configured to receive and transmit the amplified signal.
11. The portable communication device of claim 10 wherein a first amplification path operates whether a second amplification path is enabled or disabled, and the output impedance modification element associated with the first amplification path provides a high impedance in the first amplification path when the second amplification path is disabled.
12. The portable communication device of claim 10 wherein a first amplification path operates whether a second amplification path is enabled or disabled, and the output impedance modification element associated with the first amplification path provides a low impedance in the first amplification path and the output impedance modification element associated with the second amplification path provides a low impedance in the second amplification path when the second amplification path is enabled.
13. The portable communication device of claim 10 wherein the output impedance modification element associated with a first amplification path provides an impedance that is different from an impedance provided by the impedance modification element associated with a second amplification path.
14. A method for amplifying a radio frequency signal, the method comprising: providing an input RF signal to a power amplifier including one or more amplifier stages in a first amplification path and one or more amplifier stages in a second amplification path;
amplifying the input RF signal such that a first amplified signal is provided by a final stage of the power amplifier in the first amplification path and such that a second amplified signal is provided by a final stage of the power amplifier in the second amplification path;
presenting a nominal impedance to the first amplified signal and the second amplified signal; phase shifting using only one inductance the first amplified signal presented with the nominal impedance and phase shifting using only on one capacitance the second amplified signal presented with the nominal impedance to provide an output RF signal, the impedance presented to the first amplified signal and the second amplified signal substantially the same as an impedance at the output RF signal, presenting the nominal impedance being separate from phase shifting for each of the first and second amplification paths; and
operating the first amplification path whether the second amplification path is enabled or disabled.
15. The method of claim 14 wherein providing the RF input signal to the power amplifier includes:
providing the RF input signal to a phase shift element; and
altering the phase of the RF input signal such that a positive phase shifted signal is provided to the power amplifier for the first amplification path and a negative phase shifted signal is provided to the power amplifier for the second amplification path.
16. The method of claim 15 wherein providing the RF input signal to the power amplifier further includes amplifying the positive phase shifted signal to create the first amplified signal and amplifying the negative phase shifted signal to create the second amplified signal.
17. The method of claim 14 wherein phase shifting the first amplified signal presented with the nominal impedance and the second amplified signal presented with the nominal impedance is performed independent of presenting a nominal impedance to the first amplified signal and the second amplified signal.