1. A method of validating a configuration description of an automation device in a power system, wherein said description is encoded in a standardized configuration description language based on an XML schema, and wherein said description is subject to notations, requirements andor conventions which are not incorporated in said XML schema, comprising:
identifying, from Parts 7-2, 7-3 and 7-4 of an International Electrotechnical Committee 61850 standard, notations to be validated;
generating therefrom extended rules in a computer-readable format;
checking said description for conformance to the extended rules; and
issuing, in case a discrepancy is found, a notification to a user,
displaying, via a Human-Machine Interface, the notification to the user.
2. The method according to claim 1, wherein the conformance checking is executed during an engineering phase of a Substation Automation (SA) system.
3. The method according to claim 1, comprising:
checking the description for consistency with a rule generated from notations as defined in Part 7-2, 7-3 and 7-4 of the International Electrotechnical Committee 61850 standard.
4. The method according to claim 1, comprising:
checking the description for consistency with a rule representing application specific, project specific or other user defined requirements.
5. The method according to claim 1, comprising:
checking the description for consistency with power system operation principles.
6. A non-transitory computer readable medium containing a computer program for validating a configuration description of a Substation Automation (SA) system or of an Intelligent Electronic Device (IED), wherein said description is encoded in a Standardized Configuration description Language (SCL) based on an XML schema, and wherein said description is subject to notations, requirements andor conventions from Parts 7-2, 7-3 and 7-4 of an International Electrotechnical Committee 61850 standard, which are not incorporated in said XML schema, to be validated the computer program performing, when executed, the steps of:
checking said description for conformance with extended rules generated in a computer-readable format from the notations, requirements or conventions to be validated; and
issuing, in case a discrepancy is found, a notification to a user.
7. A non-transitory computer readable storage medium containing a computer program for execution by a computer for validating a configuration description of a Substation Automation system or of an Intelligent Electronic Device, wherein said description is encoded in a Standardized Configuration description Language based on an Extensible Markup Language schema, and wherein said description is subject to notations, requirements andor conventions which are not incorporated in said schema, wherein the computer program performs the steps of:
identifying, from Parts 7-2, 7-3 and 7-4 of an International Electrotechnical Committee 61850 standard, notations, to be validated;
generating there from extended rules in a computer-readable format;
checking said description for conformance to the extended rules; and
issuing, in case a discrepancy is found, a notification to a user.
8. The computer readable storage medium according to claim 7, wherein the step of conformance checking is executed during an engineering phase of the Substation Automation system.
9. The computer readable storage medium according to claim 7, wherein the computer program performs the step of:
checking the description for consistency with a rule generated from notations.
10. The computer readable storage medium according to claim 7, wherein the computer program performs the step of:
checking the description for consistency with a rule representing application specific, project specific or other user defined requirements.
11. The computer readable storage medium according to claim 7, wherein the computer program performs the step of:
checking the description for consistency with power system operation principles.
12. The method according to claim 1, wherein the automation devices are Substation Automation systems andor Intelligent Electronic Device components of the Automation systems.
13. The method according to claim 1, wherein the power system includes one or more of wind power, hydropower and Distributed Energy Resources (DER) components.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor integrated circuit having an internal monitoring function, said semiconductor integrated circuit comprising:
an internal power supply circuit for generating a driving voltage which is obtained by shifting the level of a power supply voltage;
a limiter circuit, which is operated by the input of a mode signal, for monitoring said driving voltage which is outputted from said internal power supply circuit, and for outputting an activating signal which has a first logical level until said driving voltage reaches a predetermined value and which has a second logical level after said driving voltage reaches said predetermined value, to activate and control said internal power supply circuit; and
a monitoring circuit for detecting a first change of said activating signal from said first logical level to said second logical level after the operation of said limiter circuit is started, and for outputting a monitoring signal having a constant logical level while said limiter circuit operates after said first change of said activating signal is detected.
2. A semiconductor integrated circuit as set forth in claim 1, wherein said monitoring circuit is activated in a test mode, and said monitoring signal is transferred and outputted to a first external terminal.
3. A semiconductor integrated circuit as set forth in claim 2, wherein said monitoring circuit comprises:
a comparator, to which an external power supply voltage supplied from a second external terminal is given and which is activated in said test mode, for comparing a voltage of a monitoring node which is provided for monitoring said driving voltage of said internal power supply circuit, with a reference voltage which is supplied from a third external terminal, and for outputting said monitoring signal; and
a transfer gate for transferring said monitoring signal, which is outputted from said comparator, to said first external terminal.
4. A semiconductor integrated circuit as set forth in claim 3, wherein said reference voltage supplied from said third external terminal is a voltage, the level of which varies with the elapse of time so as to cross a voltage value which is to be monitored by said monitoring node.
5. A semiconductor integrated circuit as set forth in claim 3, wherein a transfer gate driven by a boosted voltage is provided in a path for supplying said external power supply voltage from said second external terminal to said comparator.
6. A semiconductor integrated circuit as set forth in claim 3, wherein a transfer gate driven by said external power supply voltage or a voltage boosted therein is provided in a path for supplying a reference voltage from said third external terminal to said comparator.
7. A semiconductor integrated circuit as set forth in claim 2, wherein said monitoring circuit comprises:
a comparator, to which an external power supply voltage supplied from a second external terminal is given and which is activated in said test mode, for comparing a voltage of a monitoring node which is provided for monitoring said driving voltage of said internal power supply circuit, with a reference voltage which is obtained by potential-dividing said external power supply voltage, and for outputting said monitoring signal; and
a transfer gate for transferring said monitoring signal, which is outputted from said comparator, to said first external terminal.
8. A semiconductor integrated circuit as set forth in claim 7, wherein said external power supply voltage supplied from said second external terminal is a voltage, the level of which varies with the elapse of time so that said reference voltage crosses a voltage value which is to be monitored by said monitoring node.
9. A semiconductor integrated circuit as set forth in claim 7, wherein a transfer gate driven by a boosted voltage is provided in a path for supplying said external power supply voltage from said second external terminal to said comparator.
10. A semiconductor integrated circuit as set forth in claim 2, wherein said monitoring circuit comprises:
a comparator, activated in said test mode, for comparing a voltage of a monitoring node which is provided for monitoring said driving voltage of said internal power supply circuit, with a reference voltage which is supplied from a third external terminal, and for outputting said monitoring signal; and
a transfer gate for transferring said monitoring signal, which is outputted from said comparator, to said first external terminal.
11. A semiconductor integrated circuit as set forth in claim 10, wherein said reference voltage supplied from said third external terminal is a voltage, the level of which varies with the elapse of time so as to cross a voltage value which is to be monitored by said monitoring node.
12. A semiconductor integrated circuit as set forth in claim 10, wherein a transfer gate driven by an external power supply voltage or a voltage boosted therein is provided in a path for supplying a reference voltage from said third external terminal to said comparator.
13. A semiconductor integrated circuit as set forth in claim 2, wherein said monitoring circuit comprises:
a first latch circuit for detecting and holding a change of said activating signal to said first logical level immediately after an operation starts;
a second latch circuit for detecting and holding a first change of said activating signal to said second logical level after said operation starts; and
a gate circuit for obtaining said monitoring signal by a logical product of data held by said first and second latch circuits.
14. A semiconductor integrated circuit as set forth in claim 1, which further comprises:
a comparing part for comparing a predetermined voltage with a reference voltage;
an internal voltage generating part for generating an internal voltage on the basis of an output of said comparing part; and
a divided resistance part for potential-dividing into said predetermined voltage by dividing an internal voltage node with resistance,
said semiconductor integrated circuit having a test mode for determining an internal resistance value by supplying a desired trimming voltage from the outside to an external terminal connected to a first node which is an node between said internal voltage generating part and said divided resistance part, deactivating a feedback to said internal voltage generating part by the output of said comparing part, and detecting a compared result which is the output of said comparing part, in order to set said internal resistance value so as to be a desired voltage.
15. A semiconductor integrated circuit having a voltage trimming function, said semiconductor integrated circuit comprising:
a comparing part for comparing a predetermined voltage with a reference voltage;
an internal voltage generating part for generating an internal voltage on the basis of an output of said comparing part; and
a divided resistance part for potential-dividing into said predetermined voltage by dividing an internal voltage node with resistance,
said semiconductor integrated circuit having a test mode for determining an internal resistance value by supplying a desired trimming voltage from the outside to an external terminal connected to a first node which is an node between said internal voltage generating part and said divided resistance part, deactivating a feedback to said internal voltage generating part by the output of said comparing part, and detecting a compared result which is the output of said comparing part, in order to set said internal resistance value so as to be a desired voltage.
16. A semiconductor integrated circuit as set forth in claim 15, which further comprises a first reference voltage generating part for generating a reference voltage for the whole chip.
17. A semiconductor integrated circuit as set forth in claim 15, which further comprises a second reference voltage generating circuit for generating a second reference voltage, which is stepped down by level-shifting said first reference voltage, when a first reference voltage, which is a reference voltage for the whole chip, is higher than said trimming voltage which is supplied from said external terminal.
18. A semiconductor integrated circuit as set forth in claim 15, wherein said internal voltage generating part comprises:
an oscillator circuit operated by an activating signal which is outputted when said internal voltage is higher than a power supply voltage;
a booster circuit for outputting a boosted voltage, which is boosted in response to a pulse outputted from said oscillator circuit, to said first node; and
a control part for controlling a change of said oscillator circuit between activation and deactivation by a compared result, which is outputted from said comparing part, by said desired trimming voltage which is supplied from said external terminal in said test mode.
19. A semiconductor integrated circuit as set forth in claim 15, wherein said internal voltage generating part comprises:
an oscillator circuit operated by an activating signal which is outputted when said internal voltage is higher than a power supply voltage;
a booster circuit for outputting a boosted voltage, which is boosted in response to a pulse outputted from said oscillator circuit, to said first node; and
a control part for controlling a change of said booster circuit between activation and deactivation by a compared result, which is outputted from said comparing part, by said desired trimming voltage which is supplied from said external terminal in said test mode.
20. A semiconductor integrated circuit as set forth in claim 15, wherein said divided resistance part includes a variable resistor for varying a resistance value on the basis of said compared result in said test mode, said divided resistance part previously setting a set level of said trimming voltage, which is supplied from said external terminal, to be a predetermined step width, and shifting said step width upwards or downwards by a half step during a trimming test to control said set level with the precise of said half step.
21. A semiconductor integrated circuit having a function capable of generating an internal voltage by comparison with a reference voltage and fine-controlling an internal voltage value by bit data, said semiconductor integrated circuit comprising means for supplying a first voltage from the outside to an output node of an internal voltage generating circuit during a test, detecting bit data wherein a voltage ratio of an internal voltage value to a reference voltage is closest to a voltage ratio of said first voltage to a reference voltage, and fine-controlling an internal voltage in accordance with bit data during an operation other than said test.