1. A method of forming an integrated circuit, comprising:
forming a conductive layer over a first region of a semiconductor;
forming a dielectric layer comprising carbon over said conductive layer;
forming a PMD dielectric layer over said dielectric layer and said conductive layer;
forming at least one opening in said PMD dielectric layer over said conductive layer thereby exposing a region of said dielectric layer;
removing said exposed region of said dielectric layer; and
forming a first conductive region in said opening of said PMD layer wherein said first conductive region contacts said conductive layer.
2. The method of claim 1 wherein said dielectric layer is formed from a material selected from the group consisting of silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride and boron carbide.
3. The method of claim 1 wherein said removing said exposed region of said dielectric layer comprises using a RIE etch comprising chlorine.
4. The method of claim 1 further comprising forming a second dielectric layer between said conductive layer and said dielectric layer.
5. A method of forming an integrated circuit contact, comprising:
forming a conductive layer over a first region of a semiconductor;
forming a first dielectric layer over said conductive layer;
forming a second dielectric layer comprising carbon over said first conductive layer;
forming a PMD dielectric layer over said second dielectric layer and said conductive layer;
forming at least one opening in said PMD dielectric layer over said conductive layer thereby exposing a region of said second dielectric layer;
removing said exposed region of said second dielectric layer thereby exposing a region of said first dielectric layer;
removing said exposed region of said first dielectric layer; and
forming a first conductive region in said opening of said PMD layer wherein said first conductive region contacts said conductive layer.
6. The method of claim 5 wherein said second dielectric layer is formed from a material selected from the group consisting of silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride and boron carbide.
7. The method of claim 6 wherein said removing said exposed region of said second dielectric layer comprises using a RIE etch comprising chlorine.
8-10. (canceled)
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power control circuit, comprising an electronic switch electrically coupled between a power unit and an electronic device, a driving circuit electrically coupled to the electronic switch, and a mechanical switch electrically coupled to the driving circuit, wherein:
the driving circuit receives a power-on signal from the mechanical switch, and signals the electronic switch to turn on and supply power to the electronic device in accordance with the power-on signal;
the electronic device controls the driving circuit to maintain the electronic switch to be on and continue the power supply to the electronic device; and
the electronic device receives a power-off signal from the mechanical switch, and signals the driving circuit to turn off the electronic switch and discontinues the power supply to the electronic device in accordance with the power-off signal.
2. The power control circuit as claimed in claim 1, wherein the mechanical switch is a dual-contact self-returning switch or a multi-contact self-returning switch, with a first contact connects with the driving circuit and a second contact connects with the electronic device.
3. The power control circuit as claimed in claim 2, wherein the mechanical switch includes a self-returning key which can move between the first contact and the second contact by control of an external force.
4. The power control circuit as claimed in claim 3, wherein the self-returning key reaches the first contact and produces a power-on signal to the driving circuit.
5. The power control circuit as claimed in claim 4, wherein the self-returning key reaches the second contact and produces a power-off signal to the electronic device.
6. The power control circuit as claimed in claim 5, wherein the electronic switch comprises a P-channel MOS having a gate, a source and a drain, the gate connecting with the driving circuit, the source connecting with the power unit and the drain connecting with the electronic device.
7. The power control circuit as claimed in claim 6, wherein the driving circuit comprises a resistance component electrically coupled between the source and the gate of the P-channel MOS and a N-channel MOS having a gate, a source and a drain, the gate of the N-channel MOS connecting with the electronic device, the source of the N-channel MOS being grounded and the drain of the N-channel MOS connecting with the gate of the P-channel MOS.
8. The power control circuit as claimed in claim 7, wherein the first contact of the mechanical switch connects with the drain of the N-channel MOS.
9. The power control circuit as claimed in claim 6, wherein the driving circuit comprising a resistance component electrically coupled between the source and the gate of the P-channel MOS and a diode having a cathode and an anode, the cathode connecting with the gate and the anode connecting with the electronic device.
10. The power control unit as claimed in claim 9, wherein the first contact of the mechanical switch connects with the cathode of the diode.
11. The power control circuit as claimed in claim 1, wherein the electronic device receives the power-on signal via the driving circuit and boots up in accordance with the power-on signal.
12. The power control circuit as claimed in claim 1, wherein the electronic device receives the power-off signal and prepares for a shut down in accordance with the power-off signal.