1. A turbo decoder that is operable to perform parallel decoding of a turbo coded signal, the turbo decoder comprising:
a plurality of turbo decoders; and
a plurality of memories; and wherein:
the plurality of turbo decoders is operable to read from and write to the plurality of memories; and
during a first decoding iteration:
when performing natural order phase decoding processing, each turbo decoder of the plurality of turbo decoders is operable to retrieve and process information from one corresponding memory of the plurality of memories such that the corresponding memory is determined based on a contention-free mapping between the plurality of turbo decoders and the plurality of memories and a first location of the information within the one corresponding memory is based on an index function that is based on an address mapping of the one corresponding memory; and
when performing interleaved order phase decoding processing, each turbo decoder of the plurality of turbo decoders is operable to retrieve and process information from a first memory location within one first corresponding memory of the plurality of memories;
during a second decoding iteration:
when performing natural order phase decoding processing, each turbo decoder of the plurality of turbo decoders is operable to retrieve and process information from one corresponding memory of the plurality of memories such that the corresponding memory is determined based on a contention-free mapping between the plurality of turbo decoders and the plurality of memories and a second location of the information within the one corresponding memory is based on the index function that is based on the address mapping of the one corresponding memory; and
when performing interleaved order phase decoding processing, each turbo decoder of the plurality of turbo decoders is operable to retrieve and process information, from a second memory location within one second corresponding memory of the plurality of memories; and
the plurality of turbo decoders is operable to generate a best estimate of at least one bit that has been encoded into the turbo coded signal
2. The turbo decoder of claim 1, further comprising:
an anticipatory address module that is operable to generate the index function based on the address mapping of the one corresponding memory.
3. The turbo decoder of claim 1, further comprising:
a processing module that is operable to perform contention-free memory mapping between the plurality of turbo decoders and the plurality of memories during iterative decoding processing of the turbo coded signal.
4. The turbo decoder of claim 1, wherein:
during turbo encoding that generates the turbo coded signal, the turbo coded signal undergoes almost regular permutation (ARP) interleaving.
5. The turbo decoder of claim 1, wherein:
when performing turbo decoding, a turbo decoder of the plurality of turbo decoders is operable to perform almost regular permutation (ARP) interleaving on extrinsic information thereby generating \u201ca priori probability\u201d (app) information.
6. The turbo decoder of claim 1, wherein a turbo decoder of the plurality of turbo decoders includes:
an anticipatory address module that is operable to:
receive a plurality of metrics associated with the turbo coded signal;
store the plurality of metrics into the one corresponding memory; and
generate the index function based on the address mapping of the plurality of metrics within the one corresponding memory;
a first soft-insoft-out (SISO) decoder that is operable to perform SISO decoding on the plurality of metrics thereby calculating first extrinsic information;
an interleaver module that is operable to perform interleaving on the first extrinsic information thereby generating first \u201ca priori probability\u201d (app) information; and
a second SISO decoder that is operable to perform SISO decoding on the first app information thereby generating second extrinsic information;
a de-interleaver module is operable to perform de-interleaving on the second extrinsic information thereby generating second app information; and
an output processor that is operable to process most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal.
7. The turbo decoder of claim 1, wherein:
the turbo decoder employs time sharing such that the plurality of turbo decoders performed both natural order phase decoding processing and interleaved order phase decoding processing; and
when performing interleaved order phase decoding processing, addresses of the plurality of memories are accessed sequentially by the plurality of turbo decoders.
8. The turbo decoder of claim 1, wherein:
the plurality of turbo decoders includes a first number of turbo decoders; and
the plurality of memories includes a second number of memories.
9. The turbo decoder of claim 1, wherein:
the turbo decoder is implemented within a wireless personal communication device.
10. The turbo decoder of claim 1, wherein:
the turbo decoder is implemented within a communication device; and
the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
11. A turbo decoder that is operable to perform parallel decoding of a turbo coded signal, the turbo decoder comprising:
a plurality of turbo decoders;
a plurality of memories; and
an anticipatory address module that is operable to generate an index function based on an address mapping of one corresponding memory of the plurality of memories; and wherein:
the plurality of turbo decoders is operable to read from and write to the plurality of memories; and
during a first decoding iteration:
when performing natural order phase decoding processing, each turbo decoder of the plurality of turbo decoders is operable to retrieve and process information from one corresponding memory of the plurality of memories such that the corresponding memory is determined based on a contention-free mapping between the plurality of turbo decoders and the plurality of memories and a first location of the information within the one corresponding memory is based on the index function that is based on the address mapping of the one corresponding memory; and
when performing interleaved order phase decoding processing, each turbo decoder of the plurality of turbo decoders is operable to retrieve and process information from a first memory location within one first corresponding memory of the plurality of memories;
during a second decoding iteration:
when performing natural order phase decoding processing, each turbo decoder of the plurality of turbo decoders is operable to retrieve and process information from one corresponding memory of the plurality of memories such that the corresponding memory is determined based on a contention-free mapping between the plurality of turbo decoders and the plurality of memories and a second location of the information within the one corresponding memory is based on the index function that is based on the address mapping of the one corresponding memory; and
when performing interleaved order phase decoding processing, each turbo decoder of the plurality of turbo decoders is operable to retrieve and process information from a second memory location within one second corresponding memory of the plurality of memories; and
the plurality of turbo decoders is operable to generate a best estimate of at least one bit that has been encoded into the turbo coded signal
12. The turbo decoder of claim 11, wherein:
during turbo encoding that generates the turbo coded signal, the turbo coded signal undergoes almost regular permutation (ARP) interleaving; and
when performing turbo decoding, a turbo decoder of the plurality of turbo decoders is operable to perform ARP interleaving on extrinsic information thereby generating \u201ca priori probability\u201d (app) information.
13. The turbo decoder of claim 11, wherein:
the turbo decoder employs time sharing such that the plurality of turbo decoders performed both natural order phase decoding processing and interleaved order phase decoding processing; and
when performing interleaved order phase decoding processing, addresses of the plurality of memories are accessed sequentially by the plurality of turbo decoders.
14. The turbo decoder of claim 11, wherein:
the plurality of turbo decoders includes a first number of turbo decoders; and
the plurality of memories includes a second number of memories.
15. The turbo decoder of claim 11, wherein:
the turbo decoder is implemented within a wireless personal communication device.
16. The turbo decoder of claim 11, wherein:
the turbo decoder is implemented within a communication device; and
the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
17. A method for decoding a turbo coded signal, the method comprising:
receiving a turbo coded signal from a communication channel;
performing pre-processing to extract an encoded block from the turbo coded signal;
partitioning the encoded block into a plurality of sub-blocks such that each sub-block of the plurality of sub-blocks includes a corresponding plurality of data;
storing a first plurality of data of a first sub-block of the plurality of sub-blocks into a first memory bank of a plurality of memory banks;
storing a second plurality of data of a second sub-block of the plurality of sub-blocks into a second memory bank of the plurality of memory banks;
performing anticipatory address generation that includes determining an index function for accessing elements of the first plurality of data from the first memory bank and for accessing elements of the second plurality of data from the second memory bank when performing natural order phase decoding processing of the turbo coded signal;
retrieving a first index-defined element of the first plurality of data from the first memory bank and performing turbo natural order phase decoding processing thereon;
retrieving a second index-defined element of the second plurality of data from the second memory bank and performing turbo natural order phase decoding processing thereon;
retrieving a first element of the first plurality of data from the first memory bank and performing interleaved natural order phase decoding processing thereon;
retrieving a second element of the second plurality of data from the second memory bank and performing interleaved natural order phase decoding processing thereon;
turbo decoding the encoded block using a plurality of decoding processors in accordance with parallel turbo decoding processing; and
generating best estimates of information bits encoded within the turbo coded signal.
18. The method of claim 17, further comprising:
generating the index function based on the address mapping of the one corresponding memory.
19. The method of claim 17, wherein:
during turbo encoding that generates the turbo coded signal, the turbo coded signal undergoes almost regular permutation (ARP) interleaving; and further comprising:
when performing turbo decoding of the turbo coded signal, performing ARP interleaving on extrinsic information thereby generating \u201ca priori probability\u201d (app) information.
20. The method of claim 17, wherein:
the method is performed within a communication device; and
the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electrical connector comprising:
a connector body configured to receive a mating connector;
a plurality of mating conductors configured to transmit signal current, wherein each of the mating conductors includes first and second terminals;
a first open-ended conductor electrically connected to the first terminal of a first mating conductor of the plurality of mating conductors; and
a second open-ended conductor electrically connected to the second terminal of a second mating conductor of the plurality of mating conductors, wherein the first open-ended conductor is capacitively coupled to the second open-ended conductor.
2. The electrical connector of claim 1, wherein the first terminal includes an engagement portion of the respective mating conductor, the engagement portions of the mating conductors configured to engage contacts of the mating connector.
3. The electrical connector of claim 2, wherein the engagement portions are located proximate to one another at a first nodal region.
4. The electrical connector of claim 1, wherein the second terminal includes an interior portion of the respective mating conductor.
5. The electrical connector of claim 4, wherein the interior portions of the mating conductors are located proximate to one another at a second nodal region.
6. The electrical connector of claim 1, wherein the plurality of mating conductors form a first compensation region and the first and second open-ended conductors form a second compensation region, the first and second compensation regions being parallel to each other between the first and second nodal regions.
7. The electrical connector of claim 1, further including a third open-ended conductor electrically connected to the first terminal of a third mating conductor of the plurality of mating conductors and a fourth open-ended conductor electrically connected to the second terminal of a fourth mating conductor of the plurality of mating conductors, wherein the third open-ended conductor is capacitively coupled to the fourth open-ended conductor.
8. The electrical connector of claim 1, wherein the connector body has an interior chamber configured to receive the plug connector when the plug connector is inserted therein in a mating direction, the plug connector having plug contacts that engage the plurality of mating conductors in the interior chamber.
9. The electrical connector of claim 1, further comprising a printed circuit that includes the first and second open-ended conductors.
10. The electrical connector of claim 1, wherein the plurality of mating conductors form first and second differential pairs, the first differential pair of mating conductors splitting the second differential pair of mating conductors.
11. The electrical connector of claim 1, wherein the mating conductors are arranged to provide a near-end crosstalk (NEXT) compensation stage and the first and second open-ended conductors are arranged to provide a different NEXT compensation stage, the NEXT compensation stages being configured to generate compensating signals for substantially canceling or reducing a designated amount of offending crosstalk.
12. An electrical connector comprising:
a connector body configured to receive a mating connector;
a plurality of first conductors configured to transmit signal current, each of the mating conductors first and second ends, the first ends being located proximate to one another at a first nodal region, the second ends being located proximate to one another at a second nodal region, the first conductors forming a first compensation region;
a plurality of second conductors extending between the first and second nodal regions, the plurality of second conductors forming a second compensation region electrically in parallel with the first compensation region.
13. The electrical conductor of claim 12, wherein a first one of the second conductors is electrically connected to the first end of a first one of the first conductors, a second one of the second conductors is electrically connected to the second end of a second one of the first conductors, and wherein the first and second ones of the second conductors are capaitively coupled to one another.
14. The electrical conductor of claim 13, wherein the second conductors are open-ended conductors.
15. The electrical connector of claim 14, wherein the first ends of the first conductors each include an engagement portion configured to engage contacts of the first conductors.
16. The electrical connector of claim 15, wherein the engagement portions are located proximate to one another in the first nodal region.
17. The electrical connector of claim 16, wherein the second ends of the first conductors include an interior portion of the respective first conductor.
18. The electrical connector of claim 17, wherein the interior portions of the first conductors are located proximate to one another in the second nodal region.
19. The electrical connector of claim 12, further comprising a printed circuit that includes the second conductors.
20. The electrical connector of claim 12, wherein the first conductors are arranged to provide a near-end crosstalk (NEXT) compensation stage and the second conductors are arranged to provide a different NEXT compensation stage, the NEXT compensation stages being configured to generate compensating signals for substantially canceling or reducing a designated amount of offending crosstalk.