1. A computer readable medium comprising instructions for a method of partitioning a mixed signal circuit design for simulation, the method comprising:
accepting one of an analog discipline and a digital discipline that is associated with a first block of a plurality of blocks of a mixed signal circuit design;
for each domainless net of the first block, determining whether the net has a higher priority source for discipline assignment; and if not, then
assigning the accepted discipline to the net.
2. The computer readable medium of claim 1, wherein the first block is an instance of a cell, the accepted discipline is associated with the block by association with the cell, and the higher priority source is a discipline associated with the instance of the cell.
3. The computer readable medium of claim 1, wherein the first block is an instance of a cell from a library, the accepted discipline is associated with the library, and the higher priority source is a discipline associated with one of the cell and the instance.
4. The computer readable medium of claim 1, wherein the first block includes a sub-block, and the steps of determining and assigning include determining for each domainless net of the subblock whether the net has a higher priority source for discipline assignment and if not then assigning the accepted discipline to the net.
5. The computer readable medium of claim 4, wherein the higher-priority source for the sub-block discipline is a discipline associated with either that sub-block or a cell of which the sub-block is an instance.
6. The computer readable medium of claim 1, wherein the first block is one of a plurality of instances of a cell, each of the plurality is identifiable by a name having a portion common among the plurality of instances, and further comprising assigning the accepted discipline to domainless nets of instances of the plurality by matching the common portion to an identifier provided with the accepted discipline.
7. The computer readable medium of claim 1, wherein the method further comprises:
resolving, using an automated discipline resolution algorithm, disciplines for any remaining domainless nets of each of the plurality of blocks.
8. The computer readable medium of claim 1, wherein the method further comprises:
marking nets crossing a boundary of the first block for insertion of connection modules; and
resolving, using an automated discipline resolution algorithm, disciplines only for domainless nets not within the first block.
9. The computer readable medium of claim 1, wherein the method includes obtaining the one of an analog discipline and a digital discipline from a default setting.
10. The computer readable medium of claim 1, wherein the method includes obtaining a specification of the first block, the specification without discipline information for nets in the first block, and the accepted discipline is accepted from a setting provided through a mixed signal simulation tool.
11. The computer readable medium of claim 1, wherein the first block is defined by an original specification obtained through a design methodology that does not support discipline assignment, and wherein the assigning of the accepted discipline to each domainless net of the first block occurs in a local specification for the first block, separate from the original specification.
12. A computer readable medium comprising instructions for a method of partitioning, into analog and digital portions, a mixed-signal semiconductor design specified as an assembly of blocks, the method comprising:
without first using a discipline resolution algorithm to resolve domainless nets of one or more blocks in the assembly, identifying boundaries between analog and digital portions at a block level; and
indicating that discipline resolution is not to be run on the design.
13. The computer readable medium of claim 12, further comprising identifying the boundaries based on identifying which blocks were specified with a digital design language and which blocks were specified with an analog design language.
14. The computer readable medium of claim 12, wherein the analog design language is SPICE and the digital design language is selected from the group consisting of Verilog, VHDL, SystemC, and SystemVerilog.
15. The computer readable medium, of claim 12, wherein the blocks include a digital top level block hierarchically including a plurality of analog subblocks, and wherein identifying the boundaries further comprises marking IO nets between the subblocks and the top level block for insertion of connection modules.
16. The computer readable medium of claim 12, wherein the blocks include an analog top level block hierarchically including a plurality of digital subblocks, and wherein identifying the boundaries further comprises marking IO nets between the subblocks and the top level block for insertion of connection modules.
17. The computer readable medium of claim 12, wherein the method is performed responsive to a user-selectable setting, obtained from a simulation tool, that applies to the design by overrides other simulation tool provided disciplines for blocks of the design.
18. A computer readable medium comprising instructions for a method of partitioning, into analog and digital portions, a mixed-signal semiconductor design specified as an assembly of instances of blocks, the method comprising:
determining if there is a global selection to identify analog and digital portions based on information available from a design specification, then
indicating that an automated design resolution process is to be skipped; and
for each instance, determining whether the instance is at an analogdigital boundary, and if so then indicating that nets of the instance crossing the boundary are to have connection modules inserted; and
if there is no global selection, then,
determining, for each instance of the design, if there is a user-provided indication that the instance is at an analogdigital boundary, and if so then
(1) indicating that nets crossing that analogdigital boundary from the instance are to have connection modules inserted, and
(2) indicating that the automated design resolution process is to be skipped for the instance,
and if there is no such user-provided indication for the instance then, for the instance, determining whether there is a user-provided indication that all domainless nets of the instance are to be assigned either a digital or an analog discipline, and if so then assigning such discipline to each domainless net in the instance, and
running the automated design resolution process for assigning a discipline to remaining domainless nets in the design that are not within instances for which discipline resolution was indicated to be skipped.
19. A computer readable medium comprising instructions for a method of partitioning a mixed-signal semiconductor design for simulation, the design an assembly of one or more block specifications, each block specification generated by one or more design tools, each design tool referencing respective block netlists for the block specifications generated, the method comprising:
assigning, in a tool copy of the block specifications and without modifying the netlists for the block specifications, either an analog or a digital discipline to each net of each block, the discipline assigned to each net determined based on block-level discipline assignments, if available, and if not available, then based on an automated discipline resolution algorithm.
20. The computer readable medium of claim 19, wherein the block-level discipline assignment applies to a particular cell of a library of cells.
21. The computer readable medium of claim 19, wherein the block-level discipline assignment applies to a block that hierarchically includes instances of a plurality of cells, and the step of assigning includes assigning that discipline to each net of each instance, in the absence of a more particular source for a net’s discipline.
22. The computer readable medium of claim 19, wherein the block-level discipline assignment applies to a block that includes instances of a plurality of cells, and further comprising determining that an instance has been associated with a discipline assignment, and using the discipline associated with that instance, rather than the block-level discipline assignment, for assigning a discipline to each net in that instance.
23. The computer readable medium of claim 19, further comprising assigning disciplines to one or more terminals of a cell or instance, the disciplines specified through a settings obtained through a simulation tool, and not from the netlists.
24. The computer readable medium of claim 19, wherein the block-level discipline assignment is obtained from a library setting, and is applicable to all cells in that library.
25. A multimode system for partitioning a mixed signal circuit design specified as a plurality of blocks, the system comprising:
a means for determining whether to operate in a first discipline resolution mode or a second discipline resolution mode;
a means to operate in the first discipline resolution mode comprising a means for accepting a discipline associated with a first block of the plurality of blocks, and a means for assigning the discipline to each domainless net of the first block that does not have a higher priority source for discipline assignment; and
a means to operate in the second discipline resolution mode comprising a means to identify boundaries between analog and digital portions of the mixed signal circuit design without first using a discipline resolution to resolve domainless nets in the plurality of blocks.
26. The system of claim 25, further comprising:
a means for marking nets crossing a boundary of the first block for insertion of connection modules; and
a means for implementing an automated discipline resolution algorithm to resolve disciplines for domainless nets not within the first block.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A digitalanalog television receiver capable of receiving television signals in an ATSC system and an NTSC system by a single tuner, comprising:
a detecting means which detects a frequency deviation amount for each channel capable of receiving an analog television signal at a time of an automatic pre-setting;
a calculating means which calculates an average value of the frequency deviation amount on respective channels;
a storing means which stores said average value calculated by said calculating means; and
a setting means which sets channel data on the basis of said average value stored in said storing means in receiving a digital television signal.
2. A digitalanalog television receiver capable of receiving television signals in an ATSC system and an NTSC system by a single tuner, comprising:
a detecting means which detects a frequency deviation amount in receiving an analog television signal;
a storing means which stores said frequency deviation amount detected by said detecting means; and
a setting means which sets channel data on the basis of said frequency deviation amount stored in said storing means in receiving a digital television signal.
3. A digitalanalog television receiver according to claim 2, wherein said detecting means detects said frequency deviation amount upon an automatic pre-setting.
4. A digitalanalog television receiver according to claim 2 or 3, wherein
said detecting means includes an average value calculation which detects a deviation amount for each channel capable of receiving an analog television signal, and calculates an average value of the deviation amount of respective channels, and
said setting means sets said channel data on the basis of said average value.
5. A digitalanalog television receiver according to claim 4, wherein said average value calculating means includes a channel-to-channel average value calculating means which calculates a channel-to-channel average value, and said setting means sets said channel data on the basis of said channel-to-channel average value.
6. A digitalanalog television receiver according to claim 2 or 3, wherein
said detecting means includes a standard deviation calculating means which detects a deviation for each channel capable of receiving the analog television signal, and calculates a standard deviation value of the deviation amount for each channel, and
said setting means sets said channel data on the basis of said standard deviation value.
7. A control method for a digitalanalog television receiver capable of receiving television signals in the ATSC system and the NTSC system by a single tuner, comprising following steps of:
(a) detecting a frequency deviation amount in receiving an analog television signal;
(b) storing said frequency deviation amount detected in said step (a); and
(c) setting channel data on the basis of said frequency deviation amount stored in said step (b) in receiving a digital television signal.
8. A method according to claim 7, wherein said step (a) is executed upon automatic pre-setting.
9. A method according to claim 7 or 8, wherein
said step (a) includes steps of, (a1) detecting the deviation amount for each channel capable of receiving the analog television signal, and (a2) calculating an average value of the deviation amounts of channels, and
said step (c) sets said channel data on the basis of said average value.
10. A method according to claim 7 or 8, wherein
said step (a) includes steps of, (a1) detecting the frequency deviation amount for each channel capable of receiving the analog television signal, and (a3) calculating a standard deviation value of the deviation amount for said each channel, and
said step (c) sets said channel data on the basis of said standard deviation value.