1. A combination suspension rack, comprising:
a base portion;
a first overlap portion formed on a first side of the base portion;
a second overlap portion formed on a second side of the base portion;
two receiving portions each formed on the base portion, each of the two receiving portions having an insertion hole, the insertion hole of each of the two receiving portions having a wall formed with a plurality of elastic clamping plates;
wherein the two receiving portions are located on a top side and a bottom side of the base portion respectively.
2. The combination suspension rack in accordance with claim 1, wherein the base portion has a center formed with a through hole.
3. The combination suspension rack in accordance with claim 1, wherein the two receiving portions are in parallel with each other.
4. The combination suspension rack in accordance with claim 1, wherein the base portion is integrally formed with the two receiving portions.
5. A combination suspension rack, comprising:
a base portion;
a first overlap portion formed on a first side of the base portion;
a second overlap portion formed on a second side of the base portion;
two receiving portions each formed on the base portion, each of the two receiving portions having an insertion hole, the insertion hole of each of the two receiving portions having a wall formed with a plurality of elastic clamping plates;
wherein the first overlap portion is formed with an elongated combination hook, and the second overlap portion is formed with an elongated combination recess.
6. The combination suspension rack in accordance with claim 5, wherein the combination hook of the first overlap portion has a dovetail shape, and the combination recess of the second overlap portion has a dovetail shape.
7. The combination suspension rack in accordance with claim 1, wherein the first overlap portion has an end portion formed with a first catch, and the second overlap portion has an end portion formed with a second catch.
8. The combination suspension rack in accordance with claim 5, wherein the combination hook of the first overlap portion of one of two combination suspension racks is locked in the combination recess of the second overlap portion of the other one of the two combination suspension racks, so that the two combination suspension racks are combined with each other.
9. The combination suspension rack in accordance with claim 7, wherein first overlap portion and the first catch of one of two combination suspension racks is rested on the second catch and the second overlap portion of the other one of the two combination suspension racks respectively.
10. A combination suspension rack, comprising:
a base portion; and
two receiving portions each formed on the base portion, each of the two receiving portions having an insertion hole, the insertion hole of each of the two receiving portions having a wall formed with a plurality of elastic clamping plates, wherein
each of the two receiving portions includes a clamping arm formed on the base portion, and a receiving unit secured on the clamping arm;
the clamping arm of each of the two receiving portions is substantially C-shaped, and the receiving unit of each of the two receiving portions is substantially circular shaped.
11. The combination suspension rack in accordance with claim 10, wherein the insertion hole is formed in the receiving unit of each of the two receiving portions.
12. The combination suspension rack in accordance with claim 10, wherein the receiving unit of each of the two receiving portions has an outer wall formed with an annular locking groove for locking the respective clamping arm.
13. The combination suspension rack in accordance with claim 12, wherein the clamping arm of each of the two receiving portions has an inner face formed with two opposite locking holes, and the locking groove of the receiving unit of each of the two receiving portions has a periphery formed with two opposite locking blocks each locked in a respective one of the two opposite locking holes of the respective clamping arm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A split gate flash memory array, comprising:
a) a plurality of floating gates organized in rows and columns on a semiconductor substrate,
b) a plurality of buried bit lines implanted into said substrate and running the length of said columns of said floating gates,
c) each buried bit line laying beside and extending beneath said columns of said floating gates,
d) a plurality of control gates patterned in polysilicon over said rows of floating gates,
e) each control gates extending the length of each row of floating gates and forming a word line for that row of floating gates.
2. The split gate flash memory array of claim 1, wherein said buried bit lines operate as sources and drains during memory cell program and read cycles.
3. The split gate flash memory array of claim 1, wherein an insulating layer of ONO (oxide-nitride-oxide) separates said floating gates from said control gates.
4. The split gate flash memory array of claim 1, wherein voltages applied to said control gates and said buried bit lines allows said floating gates to be programmed and read.
5. The split gate flash memory array of claim 1, wherein said floating gates are erased by means of Fowler-Nordheim tunneling when a positive voltage of sufficient magnitude is applied from said buried bit lines to said control gates.
6. A method for producing a split gate multiple storage flash cell, comprising:
a) forming gate oxide on a semiconductor substrate,
b) forming an array of floating gates on surface of said substrate organized in rows and columns,
c) patterning and ion implanting buried bit lines between said columns of floating gates,
d) forming a layer of ONO (oxide-nitride-oxide) over said floating gates,
e) depositing a layer of polysilicon over surface of said substrate,
f) patterning and etching said layer of polysilicon to form control gates overlaying said rows of floating gates.
7. The method of claim 6, wherein patterning and ion implanting said buried bit lines is continuous for a length of the columns of said floating gates where each buried bit line lies adjacent to and extends partially under a first column of floating gates and is separated from a second column of floating gates.
8. The method of claim 6, wherein patterning and etching said polysilicon to form said control gates is continuous for a length of a row of floating gates and produces a word line for each row of said floating gates.
9. A method of programming a flash memory cell constructed with buried bit lines used as sources and drains, comprising:
a) applying a first positive voltage of high magnitude to a control gate overlaying a row of flash memory cells containing a first cell to be programmed,
b) applying a second voltage of moderate magnitude to a first buried bit line laying beside and partially extending under a first floating gate of said first cell,
c) applying zero volts to a second buried bit line laying beside and partially extending under a second floating gate of an adjacent second cell and separated from the first buried bit line by a channel length,
d) floating all other bit lines overlaid by said control gate,
e) connecting semiconductor substrate to zero volts,
f) maintaining voltages and connections until a predetermined threshold voltage is reached on said cell being programmed.
10. The method of programming a flash memory cell of claim 9, wherein said second buried bit line is operating as a source providing a heavy flow of electrons from which ionized electrons are injected into said first floating gate to program said first cell.
11. The method of programming a flash memory cell of claim 9, wherein said control gate overlaying a row of flash memory cells operates as a word line.
12. A method of reading a flash memory cell constructed with buried bit lines used as sources and drains, comprising:
a) applying a first positive voltage of moderate magnitude to a control gate overlaying a row of flash memory cells containing a first cell to be read,
b) applying zero volts to a first buried bit line laying beside and partially extending under a first floating gate of said first cell,
c) applying a second voltage of moderate magnitude less than said first voltage to a second buried bit line laying beside and partially extending under a second floating gate of an adjacent second cell and separated from the first buried bit line by a channel length,
d) applying zero volts to all other bit lines laying beside memory cells overlaid by said control gate,
e) connecting semiconductor substrate to zero volts,
f) reading said first cell by detecting conduction of transistor of said first cell.
13. The method of reading a flash memory cell of claim 12, wherein said first buried bit line is operating as a source and said second buried bit line is operating as a drain.
14. The method of reading a flash memory cell of claim 12, wherein said control gate overlaying a row of flash memory cells operates as a word line.
15. A method of erasing a flash memory cell constructed with buried bit lines used as sources and drains, comprising:
a) applying a high positive voltage to buried bit lines laying beside and partially under floating gates flash memory cells,
b) applying zero volts to a control gate overlaying floating gates of cells to be erased,
c) applying zero volts to semiconductor substrate,
d) maintaining voltages and connections until threshold of said cells fall below a predetermined threshold voltage level.
16. The method of erasing a flash memory cell of claim 15, wherein erasing said floating gates is done by means of Fowler-Nordheim tunneling.
17. The method of erasing a flash memory cell of claim 15, wherein applying said high positive voltage to said buried bit lines erases only those cells adjacent to said buried bit lines and laying under said control gate.