1. An LSI (Large-Scale Integrated circuit) designing system for carrying out layout design by inputting information about configurations of circuits internally formed in each LSI comprising MIS (Metal Insulator Semiconductor) transistors, comprising:
a gate size correcting unit to detect a wiring segment expected to cause an antenna damage to a gate insulating film of each of said MIS transistors due to an antenna effect that said wiring segment absorbs electric charges generated during plasma etching processes and to correct, based on a result from specified simulation or from specified experiment, an area of a gate electrode of each of said MIS transistors connected to the detected wiring segment so as to become a value that enables the prevention of said antenna damage.
2. The LSI circuit designing system according to claim 1, wherein said gate size correcting unit comprises:
a sizing candidate table creating unit to store correction candidate values to be used for correction of an area of said gate electrode in ascending order for every type of a cell corresponding to said circuit configurations to create a sizing candidate cell table;
an antenna error net detecting unit to detect a net having a wiring segment expected to cause said antenna damage;
a gate pincell recognizing unit to recognize a gate pin connected to said net and a type of a cell corresponding to said gate pin; and
a cell sizing unit to judge whether or not said antenna damage is able to be prevented by using said correction candidate values in ascending order stored in said sizing candidate cell table based on a specified judgment standard and to correct an area of said gate electrode by using a minimum value that enables the prevention of said antenna damage.
3. The LSI circuit designing system according to claim 2, wherein said LSI comprises a plurality of wiring layers and wherein said antenna error net detecting unit is configured to detect a net having a wiring segment expected to cause said antenna damage and wherein said cell sizing unit is configured to judge, for every wiring layer, whether a ratio of a sum total of metal areas to a sum total of an area of said gate electrode contained in a wiring layer is not larger than a predetermined reference value and judges, when said ratio is not larger than said reference value, said antenna damage as being able to be prevented.
4. An LSI circuit designing system for carrying out layout design by inputting information about configurations of circuits internally formed in each LSI comprising MIS transistors, comprising:
an antenna error preventing unit to detect a wiring segment expected to cause antenna damage to a gate insulating film of each of said MIS transistors due to an antenna effect in which said wiring segment absorbs electric charges generated during plasma etching processes and to connect, based on a result from a specified simulation or from a specified experiment and via said wiring segment, an antenna error preventing cell to provide a specified gate area and to diffuse electric charges absorbed in said wiring segment to a gate electrode of each of said MIS transistors connected to the detected wiring segment in number that enables the prevention of the antenna damage.
5. The LSI system according to claim 4, wherein said antenna error preventing unit comprises:
an antenna error net detecting unit to detect a net having a wiring segment expected to cause said antenna damage; and
an antenna error preventing cell connecting unit to connect said antenna error preventing cell to the detected wiring segment.
6. The LSI circuit designing system according to claim 5, wherein said LSI comprises a plurality of wiring layers and wherein said antenna error net detecting unit is configured to detect, for every said wiring layer, a net having a wiring segment expected to cause said antenna damage and wherein said antenna error preventing cell connecting unit is configured to connect, for every said wiring layer, said antenna error preventing cell to each of detected said wiring segments.
7. The LSI circuit designing system according to claim 4, wherein said antenna error preventing cell is configured so that its input terminal is connected to a gate circuit having a specified gate area, an anode of a first diode to diffuse electric charges absorbed in said wiring segment, and a cathode of a second diode to diffuse the electric charges.
8. An antenna damage preventing method to be used for an LSI circuit designing system for carrying out layout design by inputting information about configurations of circuits internally formed in each LSI comprising MIS transistors and for preventing antenna damage occurring in a gate insulating film of each MIS transistor, said method comprising:
detecting a wiring segment expected to cause an antenna damage to a gate insulating film of each of said MIS transistors due to an antenna effect that said wiring segment absorbs electric charges generated during plasma etching processes; and
correcting, based on a result from a specified simulation or from a specified experiment, an area of a gate electrode of each of said MIS transistors connected to the detected wiring segment so as to become a value that enables the prevention of said antenna damage.
9. The antenna damage preventing method according to claim 8, further comprising:
sizing candidate table creating processing for storing correction candidate values to be used for correction of an area of said gate electrode in ascending order for every type of a cell corresponding to said circuit configurations to create a sizing candidate cell table;
antenna error net detecting processing for detecting a net having a wiring segment expected to cause said antenna damage;
gate pincell recognizing processing for recognizing a gate pin connected to said net and a type of a cell corresponding to said gate pin; and
cell sizing processing for judging whether or not said antenna damage is able to be prevented by using said correction candidate values stored in said sizing candidate cell table based on a specified judgment standard and for correcting an area of said gate electrode by using a minimum value that enables the prevention of said antenna damage.
10. The antenna damage preventing method according to claim 9, wherein said LSI comprises a plurality of wiring layers and wherein said antenna error net detecting unit is configured to detect a net having a wiring segment expected to cause said antenna damage and wherein said cell sizing unit is configured to judge, for every wiring layer, whether a ratio of a sum total of metal areas to a sum total of an area of said gate electrode contained in a wiring layer is not larger than a predetermined reference value and judges, when said ratio is not larger than said reference value, said antenna damage as being able to be prevented.
11. An antenna damage preventing method to be used for an LSI circuit designing system for carrying out layout design by inputting information about configurations of circuits internally formed in each LSI comprising MIS transistors and for preventing antenna damage occurring in a gate insulating film of each of said MIS transistors, said method comprising:
detecting a wiring segment expected to cause antenna damage to a gate insulating film of each of said MIS transistors due to an antenna effect in which said wiring segment absorbs electric charges generated during plasma etching processes; and
connecting, based on a result from specified simulation or from a specified experiment and via said wiring segment, an antenna error preventing cell to provide a specified gate area and to diffuse electric charges absorbed in said wiring segment to a gate electrode of each of said MIS transistors connected to the detected wiring segment in number that enables the prevention of the antenna damage.
12. The antenna damage preventing method according to claim 11, further comprising:
antenna error net detecting processing for detecting a net having a wiring segment expected to cause said antenna damage; and
antenna error preventing cell connecting processing for connecting said antenna error preventing bell to the detected wiring segment.
13. The antenna damage preventing method according to claim 12, wherein said LSI comprises a plurality of wiring layers and, in said antenna error net detecting processing, a net having a wiring segment expected to cause said antenna damage is detected and, in said antenna error preventing cell connecting processing, said antenna error preventing cell is connected to the detected wiring segment.
14. An antenna damage prevention controlling program to be executed by a computer for realizing functions of an LSI circuit designing system for carrying out layout design by inputting information about configurations of circuits internally formed in each LSI comprising MIS (Metal Insulator Semiconductor) transistors, comprising:
a gate size correcting unit to detect a wiring segment expected to cause an antenna damage to a gate insulating film of each of said MIS transistors due to an antenna effect that said wiring segment absorbs electric charges generated during plasma etching processes and to correct, based on a result from specified simulation or from specified experiment, an area of a gate electrode of each of said MIS transistors connected to the detected wiring segment so as to become a value that enables the prevention of said antenna damage.
15. An LSI (Large,-Scale Integrated circuit) designing system for carrying out layout design by inputting information about configurations of circuits internally formed in each LSI comprising MIS (Metal Insulator Semiconductor) transistors, comprising:
a gate size correcting means to detect a wiring segment expected to cause an antenna damage to a gate insulating film of each of said MIS transistors due to an antenna effect that said wiring segment absorbs electric charges generated during plasma etching processes and to correct, based on a result from specified simulation or from specified experiment, an area of a gate electrode of each of said MIS transistors connected to the detected wiring segment so as to become a value that enables the prevention of said antenna damage.
16. The LSI circuit designing system according to claim 15, wherein said gate size correcting means comprises:
a sizing candidate table creating means to store correction candidate values to be used for correction of an area of said gate electrode in ascending order for every type of a cell corresponding to said circuit configurations to create a sizing candidate cell table;
an antenna error net detecting means to detect a net having a wiring segment expected to cause said antenna damage;
a gate pincell recognizing means to recognize a gate pin connected to said net and a type of a cell corresponding to said gate pin; and
a cell sizing means to judge whether or not said antenna damage is able to be prevented by using said correction candidate values in ascending order stored in said sizing candidate cell table based on a specified judgment standard and to correct an area of said gate electrode by using a minimum value that enables the prevention of said antenna damage.
17. The LSI circuit designing system according to claim 16, wherein said LSI comprises a plurality of wiring layers and wherein said antenna error net detecting means is configured to detect a net having a wiring segment expected to cause said antenna damage and wherein said cell sizing means is configured to judge, for every wiring layer, whether a ratio of a sum total of metal areas to a sum total of an area of said gate electrode contained in a wiring layer is not larger than a predetermined reference value and judges, when said ratio is not larger than said reference value, said antenna damage as being able to be prevented.
18. An LSI circuit designing system for carrying out layout design by inputting information about configurations of circuits internally formed in each LSI comprising MIS transistors, comprising:
an antenna error preventing means to detect a wiring segment expected to cause antenna damage to a gate insulating film of each of said MIS transistors due to an antenna effect in which said wiring segment absorbs electric charges generated during plasma etching processes and to connect, based on a result from a specified simulation or from a specified experiment and via said wiring segment, an antenna error preventing cell to provide a specified gate area and to diffuse electric charges absorbed in said wiring segment to a gate electrode of each of said MIS transistors connected to the detected wiring segment in number that enables the prevention of the antenna damage.
19. The LSI system according to claim 18, wherein said antenna error preventing means comprises:
an antenna error net detecting means to detect a net having a wiring segment expected to cause said antenna damage; and
an antenna error preventing cell connecting means to connect said antenna error preventing cell to the detected wiring segment.
20. The LSI circuit designing system according to claim 19, wherein said LSI comprises a plurality of wiring layers and wherein said antenna error net detecting means is configured to detect, for every wiring layer, a net having a wiring segment expected to cause said antenna damage and wherein said antenna error preventing cell connecting means is configured to connect, for every wiring layer, said antenna error preventing cell to each of detected wiring segments.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.
What is claimed is
1. An electronic ballast control for controlling a power switch in an electronic ballast to switch power to a load, comprising:
a storage device for storing parameters to operate ballast control components;
a control device coupled to the storage device for reading parameters from the storage device and providing the parameters to ballast control components;
an oscillator coupled to the control device for receiving parameters from the control device and providing an oscillation signal based on the received parameters;
an output section coupled to the oscillator and operable to receive the oscillation signal and produce signals for operating the power switch.
2. The control according to claim 1, further comprising a minimum frequency signal applied to the oscillator to determine a minimum oscillation frequency provided by the oscillator.
3. The control according to claim 2, further comprising a passive component coupled to the oscillator to provide the minimum frequency signal.
4. The control according to claim 1, further comprising an input device coupled to the storage device for inputting data to the storage device.
5. The control according to claim 4, further comprising an input data to the input device, wherein the input device is operable to translate the input data to a format suitable for input to the storage device.
6. The control according to claim 1, wherein the control is implemented on an integrated circuit.
7. The control according to claim 1, wherein the storage device is a digital storage device.
8. The control according to claim 1, wherein the control device is a digital control device.
9. The control according to claim 1, wherein the oscillator is a digital oscillator.
10. The control according to claim 1, wherein the control device or the controller is programmable with parameters from the storage device, whereby the control is operable to obtain variable operating characteristics based on parameter programming.
11. The control according to claim 9, further comprising a DAC in the oscillator for converting in input digital signal to an analog signal, whereby the oscillation frequency is related to the analog signal.
12. A method of operating an electronic ballast, comprising:
storing data in a storage device related to ballast control parameters;
reading data from the storage device to obtain parameters for operating the ballast control; and
applying the parameters to ballast control components to obtain selected operating points for the components, whereby the ballast control outputs a control signal based on a selection of parameters applied to the components.
13. The method according to claim 12, wherein storing data in the storage device further comprises applying a storage input signal to an input coupled to the storage device; and
applying an enable signal to another input coupled to the storage device to enable the data signal to be accepted and stored by the storage device.
14. The method according to claim 12, wherein the data is digital data.
15. The method according to claim 14, further comprising selectively applying the digital data to the ballast control components to obtain operating set points for the ballast control.
16. The method according to claim 12, further comprising applying a minimum frequency signal to an oscillator component in the ballast control to determine a relative minimum switching frequency for the ballast control.
17. The method according to claim 12, further comprising providing a buffered voltage bias in the ballast control that is decoupled from an AC input.
18. The method according to claim 12, further comprising counting a number of events in the ballast control to determine when the number of events reach a predetermined value in a specified time period.
19. The method according to claim 12, further comprising timing one or more events to determine if a predetermined time duration is achieved for the one or more events.
20. A ballast control IC, comprising:
a digital memory for storing control parameters;
a digital controller coupled to the memory for reading parameters from the memory;
a digital oscillator coupled to the controller for receiving a digital oscillation set point and providing an oscillation signal based on the set point.
21. The IC according to claim 20, further comprising a digital counter for counting a number of events and providing an indication if a predetermined count is reached.
22. The IC according to claim 20, further comprising a timer in the controller for timing an event and outputting a signal if a predetermined duration of time passes related to the event.