1. A nano-construct comprising
(a) a metal or metal alloy nanoshell formed around a core material, and
(b) a bioactive agent,
wherein the core material comprises a material selected from the group consisting of a liposome, a polymersome, and a hybrid vesicle comprising both lipid and polymer-based constituents,
wherein the core material further comprises dielectric material, which comprises magnetic ceramic particles.
2. The nano-construct of claim 1, wherein the nanoshell is a gold nanoshell.
3. The nano-construct of claim 1, comprising a large unilamellar vesicle,
wherein the large unilamellar vesicle encapsulates the nanoshell and the bioactive agent.
4. The nano-construct of claim 1, wherein the core material is a small unilamellar vesicle encapsulating the bioactive agent.
5. The nano-construct of claim 1, wherein the nanoshell is a gold nanoshell having a thickness in the range between about 5 and about 25 nm.
6. The nano-construct of claim 1, wherein the core material is a liposome having a size in the range between about 150 nm to about 200 nm.
7. The nano-construct of claim 1, wherein the metal or metal alloy nanoshell surrounding the core is porous to the bioactive agent once it is released from the core material.
8. The nano-construct of claim 2, wherein the gold nanoshell surrounds the core of a dielectric material, and
wherein a plurality of these gold shells are conjugated to the surface of the core material, which contains the bioactive agent.
9. The nano-construct of claim 1, wherein the core material comprises a peptide, a protein, or a combination of these.
10. The nano-construct of claim 1, further comprising a targeting molecule on the surface of the nano-construct.
11. The nano-construct of claim 10, wherein the targeting molecule is a surface-conjugated ligand against one or more receptors on an inflamed endothelium.
12. The nano-construct of claim 1 in a formulation suitable for systemic delivery or local delivery into a human being.
13. The nano-construct of claim 12, wherein the systemic delivery is injection.
14. The nano-construct of claim 12, wherein the local delivery is delivery by a device comprising a catheter.
15. The nano-construct of claim 1, wherein the bioactive agent is paclitaxel, docetaxel, estradiol, 17-beta-estradiol, nitric oxide donors, super oxide dismutases, super oxide dismutases mimics, 4-amino-2,2,6,6-tetramethylpiperidine-1-oxyl, tacrolimus, dexamethasone, rapamycin, 40-O-(2-hydroxy)ethyl-rapamycin, 40-O-(3-hydroxy)propyl-rapamycin, 40-O-2-(2-hydroxy)ethoxyethyl-rapamycin, 40-O-tetrazole-rapamycin, 40-epi-(N1-tetrazolyl)-rapamycin, \u03b3-hirudin, clobetasol, pimecrolimus, imatinib mesylate, or midostaurin, or prodrugs, or combinations of these.
16. A method of forming a nano-construct according to claim 1, comprising:
providing a core material selected from a liposome, a polymerosome, a hybrid vesicle,
forming a nanoshell around the core material.
17. The method of claim 16, wherein the core material encapsulates a bioactive agent.
18. The method of claim 16, wherein the formed nanoshell has porosity.
19. The method of claim 16, wherein the core material is a liposome.
20. The method of claim 16, wherein the nanoshell is a gold nanoshell having a thickness in the range between about 5 and about 25 nm.
21. The method of claim 16, wherein the liposome has a size in the range between about 150 nm to about 200 nm.
22. The method of claim 16, wherein the core material comprises a peptide, a protein, or a combination of these.
23. The method of claim 16, wherein the nano-construct comprises a targeting molecule on the surface of the nano-construct.
24. The method of claim 23, wherein the targeting molecule is a suface-conjugated ligand against receptors on an inflamed endothelium.
25. The method of claim 16, wherein the nano-construct is in a formulation suitable for systemic delivery or local delivery into a human being.
26. The method of claim 25, wherein the systemic delivery is injection.
27. The method of claim 25, wherein the local delivery is delivery by a device comprising a catheter.
28. The method of claim 16, wherein the bioactive agent is paclitaxel, docetaxel, estradiol, 17-beta-estradiol, nitric oxide donors, super oxide dismutases, super oxide dismutases mimics, 4-amino-2,2,6,6-tetramethylpiperidine-1-oxyl, tacrolimus, dexamethasone, rapamycin, rapamycin derivatives, 40-O-(2-hydroxy)ethyl-rapamycin, 40-O-(3-hydroxy)propyl-rapamycin, 40-O-2-(2-hydroxy)ethoxyethyl-rapamycin, 40-O-tetrazole-rapamycin, 40-epi-(N1-tetrazolyl)-rapamycin, \u03b3-hirudin, clobetasol, pimecrolimus, imatinib mesylate, or midostaurin, or prodrugs, or combinations of these.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for using a system controller disposed in a single chip having a first clock domain and a second clock domain, the method comprising:
receiving a read request in the first clock domain of a host interface of said system controller having a first clock rate;
passing said read request into the second clock domain of a memory controller of said system controller associated with accessing a memory via a memory bus, said second clock domain having a second clock rate;
in said second clock domain, said read request triggering said memory controller to assert a read command to said memory via said memory bus to fulfill said read request and the read request further triggering said memory controller to also send a delay-adjusted alarm message in said second clock domain to said host interface such that the delay-adjusted alarm message includes an indication of a time in the future when data to fulfill said read request will be returned from said memory to said first clock domain in response to the read command asserted on said memory bus and the indication is adjusted based on a time delay between said read request and said data becoming present and stable in said host interface,
wherein triggering said memory controller to send said delay-adjusted alarm message includes calculating said time delay using said memory controller;
in said first clock domain, said host interface receiving said alarm message at a time before the data is ready for transfer, converting said alarm message in said second clock domain into an alarm message in said first clock domain, and dynamically monitoring attributes of said read request to generate a programmable offset to said alarm message in said first clock,
wherein said host interface utilizes said alarm message to schedule a data ready signal to transfer data at an earliest safe clock cycle in the first clock domain without requiring a synchronous handover within the chip of data fulfilling said read request between said clock domains prior to scheduling the data ready signal.
2. The method of claim 1, further comprising: maintaining a first counter in said first clock domain and a second counter in said second clock domain such that an alarm time in said second clock domain is interpreted in said first clock domain.
3. The method of claim 1, wherein said first clock domain is associated with a front side bus interface and said receiving a read request comprises receiving a read request on said front side bus interface from a central processing unit.
4. The method of claim 1, wherein said delay occurs in response to at least one of: an inbound memory bus delay, a CAS latency associated with said memory, or an outbound memory bus delay.
5. The method of claim 1, further comprising accounting for a latency of said first clock domain to respond to said alarm message.
6. The method of claim 1, further comprising sampling read data from said memory.
7. The method of claim 1, wherein dynamically monitoring attributes of said read request to generate a programmable offset comprises monitoring a data size of said read request.
8. A system controller disposed in a chip for a host to read stored data, comprising:
a host interface in the chip disposed in a first clock domain having a first clock rate;
a memory controller in the chip for interfacing with a memory, said memory controller disposed in a second clock domain having a second clock rate associated with said memory, said memory controller receiving read requests passed on from said host interface;
a data return path for data to be returned from said memory to said host interface;
said memory controller being triggered by a received read request to assert a read command to said memory via a memory bus to fulfill said read request and the read request further triggering said memory controller to also send a delay-adjusted alarm message in said second clock domain to said host interface such that the delay-adjusted alarm message includes an indication,
wherein said indication is a calculated value of a time in the future when data to fulfill said read request will be returned from said memory to said first clock domain in response to the read command asserted on said memory bus
and said indication is adjusted based on a time delay between said read request and said data becoming present and stable in said host interface; and
said host interface receiving said alarm message in said second clock domain at a time before the data is ready for transfer, and dynamically monitoring attributes of said read request to generate a programmable offset to said alarm message in said first clock domain,
wherein said host interface utilizes said alarm message to schedule a data ready signal to transfer data at an earliest safe clock cycle in the first clock domain without requiring a synchronous handover within the chip of data fulfilling said read request between said clock domains prior to scheduling the data ready signal.
9. The system controller of claim 8, wherein said host interface comprises a front side bus interface.
10. The system controller of claim 8, wherein said host interface comprises a data return for receiving data from said data return path.
11. The system controller of claim 10, wherein said safe clock cycle comprises an earliest clock cycle in said first clock domain for which data to fulfill said particular read request will be returned and available.
12. The system controller of claim 11, wherein said data return determines said earliest clock cycle based upon said alarm message and a size of said particular read request.
13. The system controller of claim 11, wherein said memory is a random access memory having DQ and DQS pins carrying DQ and DQS signals and said data path samples said DQ and DQS signals.
14. The system controller of claim 8, wherein each clock domain is locked to the other with a fixed ratio.
15. The system controller of claim 8, wherein each clock domain maintains a local counter, whereby an alarm time in said second clock domain is adapted to be translated into a time in said first clock domain.
16. The system controller of claim 8, wherein said attributes of said read request comprise a data size of said read request.
17. A chip acting as a North Bridge interface between a central processing unit and a memory, the chip comprising:
a host interface in the chip having a front side bus interface disposed in a front side bus clock domain having a first clock rate, said front side bus interface adapted to receive read requests from said central processing unit and return data to said central processing unit;
a memory controller in the chip for interfacing with said memory, said memory controller disposed within a memory clock domain having a second clock rate, said memory controller receiving read requests from said front side bus interface;
a data return path for returning data from said memory to a data return within said front side bus clock domain;
said memory controller being triggered by a received read request to assert a read command to said memory via a memory bus to fulfill said read request and the read request further triggering said memory controller to also send a delay-adjusted alarm message in said memory clock domain to said host interface such that the delay-adjusted alarm message includes an indication of a transfer time in the future in the front side bus clock domain when data to fulfill said read request will be returned from said memory to said front side bus clock domain in response to the read command asserted on said memory bus and the indication is adjusted based on a time delay between said read request and said data becoming present and stable in said host interface, said memory controller configured to calculate said time delay, the transfer time corresponding to a safe clock cycle in said front side bus clock domain; and
said data return receiving said alarm message in said memory clock domain at a time before the data is ready for transfer, converting said alarm message in said memory clock domain into an alarm message in said front side bus clock domain, and dynamically monitoring attributes of said read request to generate a programmable offset to said alarm message in said front side bus clock domain,
wherein said host interface utilizes said alarm message in said front side bus clock domain to schedule a data ready signal to transfer data at an earliest safe clock cycle in the first clock domain without requiring a synchronous handover in the chip of data fulfilling said read request between said clock domains prior to scheduling the data ready signal.
18. The chip of claim 17, wherein said safe clock cycle comprises an earliest clock cycle in said front side bus clock domain for which data to fulfill said particular read request will be returned and available.
19. The chip of claim 18, wherein said data return generates a data ready signal for said earliest clock cycle.
20. The chip of claim 17, wherein a first wall clock is maintained in said memory controller and a second wall clock is maintained in said data return, said first and second wall clocks being synchronized at some initial time and operated in phase at a rational multiple of each other, whereby a time in said memory controller domain is adapted to be interpreted in said front side bus domain.
21. The chip of claim 17, wherein said attributes of said read request comprise a data size of said read request.