What is claimed is:
1. A power on reset signal generating circuit arrangement comprising:
delay means for generating a reset release signal delayed in time by a delay from a time at which a voltage between two voltage terminals has recovered to a first voltage level during a recovery of said voltage from essentially zero volts.
2. The circuit arrangement according to claim 1, wherein said delay means forms no DC current paths between said two voltage terminals.
3. The circuit arrangement according to claim 2, wherein said delayed reset release signal delay is derived from said recovery of said voltage.
4. The circuit arrangement according to claim 2, wherein said delay time is greater than a minimum reset release delay time.
5. The circuit arrangement according to claim 4, wherein said means comprises a capacitor wherein said minimum reset release delay time is responsive to said capacitor.
6. The circuit arrangement according to claim 4, further comprising a voltage-controlled device responsive to a voltage developed across said capacitor.
7. The circuit arrangement according to claim 4, further comprising a voltage clamping device coupled between one end of said fixed capacitor and one of said two terminals, said voltage clamping device configured to prevent a voltage difference greater than about 1 diode drop between said one end of said fixed capacitor and said one of said two terminals.
8. The circuit arrangement according to claim 1, wherein circuit elements are selected from the group consisting of 3-terminal transistors and capacitors.
9. The circuit arrangement according to claim 1, wherein resistor circuit elements are not connected between power supply terminals.
10. The circuit arrangement according to claim 8, wherein said voltage level is determined by values of electrical parameters characteristic of said elements.
11. The circuit arrangement according to claim 10, wherein said electrical parameters include MOS threshold voltage values.
12. The circuit arrangement according to claim 1, including a buffer isolating said delay means from circuits receiving said delayed signal.
13. The circuit arrangement according to claim 1, comprising a voltage controlled current source.
14. The circuit arrangement according to claim 1, comprising a voltage divider coupled between the two voltage terminals.
15. The circuit arrangement according to claim 14, wherein said voltage divider is a capacitor having one end connected to one of said voltage terminals and the other end connected to a first common connection with a control electrode and one of two controlled current conducting electrodes of a first 3-electrode current controlled device, in which the other current conducting electrode of said device is connected to said other of said voltage terminals.
16. The circuit arrangement according to claim 15, comprising a second 3-electrode current conducting device having a second control electrode and two second controlled current conducting electrodes wherein said second control electrode is connected to said first common connection, and one of said two second controlled current conducting electrodes is connected to said one end of said capacitor.
17. The circuit arrangement according to claim 16, comprising a second capacitor connected at one end to said other of said two second controlled current conducting electrodes and connected at its other end to said other of said voltage terminals.
18. The circuit arrangement according to claim 17, comprising a switching circuit having an input and an output responsive to said input in which said input is connected to said one end of said other of said two second controlled current conducing electrodes.
19. The circuit arrangement according to claim 18, in which said switching circuit defines a switching threshold value.
20. The circuit arrangement according to claim 19, in which said delay means comprises said switching threshold value, said capacitor, said first 3-electrode current controlled device, said second 3-electrode current controlled device, said first capacitor, and said second capacitor.
21. The circuit arrangement according to claim 17, comprising discharge means for discharging said first common connection to said other voltage terminal when said other voltage terminal is discharged from an initial voltage toward zero volts.
22. The circuit arrangement according to claim 17, comprising discharge means for discharging said one end of said other of said second capacitor to said other voltage terminal when said other voltage terminal is discharged from an initial voltage toward zero volts.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A portable, monoblock air conditioner comprising:
an evaporator positioned over a condenser, said condenser comprising heat transfer fins; and
a partition positioned between said evaporator and said condenser, said partition formed with openings arranged for condensate to flow from said evaporator over said heat transfer fins of said condenser, wherein there are more than one of said openings over each heat transfer fin.
2. The portable, monoblock, one-ducted air conditioner according to claim 1, wherein adjacent rows of openings over the heat transfer fins are staggered with respect to each other.
3. The portable, monoblock, one-ducted air conditioner according to claim 1, wherein heat transfer fins of said condenser comprise a hydrophilic coating.
4. The portable, monoblock, one-ducted air conditioner according to claim 1, wherein the rate at which said condensate is formed and flows through said openings of said partition does not exceed the rate at which said condenser is capable of evaporating said condensate into vapor, so that substantially all of said condensate is evaporated by said condenser into vapor.
5. The portable, monoblock, one-ducted air conditioner according to claim 1, wherein said partition is constructed of a thermal insulating material.
6. The portable, monoblock, one-ducted air conditioner according to claim 1, wherein said partition is constructed of a vibration damping material.