1. Apparatus comprising:
a transaction response receiver to receive a transaction response from one of one or more transaction slaves via interconnect circuitry, said transaction response including payload data and control check data; and
control checking circuitry:
(i) to hold, prior to receipt of said transaction response, expected data corresponding to correct control of transmission of a transaction associated with said transaction response;
(ii) to check, following receipt of said transaction response, if said control check data matches said expected data; and
(iii) if said control check data does not match said expected data, then to trigger reporting of and action upon a detected error.
2. Apparatus as claimed in claim 1, wherein said transmission control checking circuitry is associated with a given transaction master of one or more transaction masters and said expected value includes a transaction identifier of a transaction issued by said given transaction master.
3. Apparatus as claimed in claim 2, comprising a transaction identifier generator to generate said transaction identifier for said given transaction master.
4. Apparatus as claimed in claim 2, wherein said transaction identifier is a unique transaction identifier having a unique value among unique transaction identifiers concurrently in use for pending transactions.
5. Apparatus as claimed in claim 2, wherein said transaction identifier is at least part of a sideband signal accompanying said transaction and said interconnect circuitry is configured to route said transaction independently of said transaction identifier.
6. Apparatus as claimed in claim 2, wherein:
(i) said control check data matching said transaction identifier corresponds to return of said transaction response to said given transaction; and
(ii) said control check data not matching said transaction identifier corresponds to receipt of a misdirected transaction response intended for a transaction master other than said given transaction master.
7. Apparatus as claimed in claim 2, wherein said transaction identifier is a combination of:
(i) a unique identifier value for said given transaction master among said one or more transaction masters; and
(ii) a number unique among concurrently pending transactions issued by said given transaction master.
8. Apparatus as claimed in claim 7, wherein said given transaction master includes an address buffer to store addresses associated with pending transactions within a plurality of storage locations of said address buffer and said number is determined by which of said plurality of storage location stores an address corresponding to said transaction.
9. Apparatus as claimed in claim 1, wherein said transaction results in a response sequence comprising a plurality of transaction responses returned to said given transaction master.
10. Apparatus as claimed in claim 9, wherein said control check data is sequence check data and said control check data matching said expected data corresponds to receipt of an expected next transaction response within said response sequence.
11. Apparatus as claimed in claim 10, wherein said control check data includes a bit that alternates in value with each successive transaction response within said response sequence.
12. Apparatus as claimed in claim 1, wherein said transaction is a data read and said transaction response includes read data.
13. Apparatus as claimed in claim 2, wherein said transaction results in a response sequence comprising a plurality of transaction responses returned to said given transaction master and said transaction identifier is associated with each of said plurality of transaction responses.
14. Apparatus as claimed in claim 1, wherein said transaction response includes an error detecting code and further comprising error detecting circuitry to use said error detecting code to detect at least some errors in said payload data.
15. Apparatus comprising:
a transaction request receiver to receive a read transaction request from a given transaction master of one or more transaction masters via interconnect circuitry, said read transaction request including control check data for triggering reporting of and action upon a detected error;
a transaction response generator to generate a read transaction response corresponding to said transaction request and including read data and said control check data; and
a transaction response transmitter to transmit said transaction response to said given transaction master.
16. Apparatus comprising:
a transaction request receiver to receive a write transaction request from a given transaction master of one or more transaction masters via interconnect circuitry, said write transaction request including request control check data; and
a write data receiver:
(i) to receive write data accompanied by write data control check data;
(ii) to check that said write data corresponds to said write transaction request by checking that said write data control check data matches said request control check data; and
(iii) if said write data control check data does not match said request control check data, then to trigger reporting of and action upon a detected error.
17. Apparatus comprising:
a transaction request receiver to receive a write transaction request for a sequence of write data transfers via interconnect circuitry, each of said write data transfers including respective sequence check data; and
a write data receiver:
(i) to receive a received write data transfer accompanied by received sequence check data;
(ii) to check that said received write data transfer corresponds to a next expected write data transfer by checking that said received sequence check data matches expected next sequence check data; and
(iii) if said received write data transfer does not match said next expected write data transfer, then to trigger reporting of and action upon a detected error.
18. A transaction master comprising apparatus as claimed in claim 1.
19. A transaction slave comprising apparatus as claimed in claim 15.
20. A transaction slave comprising apparatus as claimed in claim 16.
21. A transaction slave comprising apparatus as claimed in claim 17.
22. Apparatus for processing data comprising one or more transaction masters connected via interconnect circuitry to one or more transaction slaves and comprising apparatus as claimed in claim 1.
23. Apparatus comprising:
transaction response receiving means for receiving a transaction response from one of one or more transaction slaves via interconnect circuitry, said transaction response including payload data and control check data; and
control checking means for:
(i) holding, prior to receipt of said transaction response, expected data corresponding to correct control of transmission of a transaction associated with said transaction response;
(ii) detecting, following receipt of said transaction response, if said control check data matches said expected data; and
(iii) if said control check data does not match said expected data, then to trigger reporting of and action upon a detected error.
24. A method comprising the steps of:
receiving a transaction response from one of one or more transaction slaves via interconnect circuitry, said transaction response including payload data and control check data; and
holding, prior to receipt of said transaction response, expected data corresponding to correct control of transmission of a transaction associated with said transaction response;
detecting, following receipt of said transaction response, if said control check data matches said expected data; and
if said control check data does not match said expected data, then triggering reporting of and action upon a detected error.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An analog temperature measurement circuit comprising:
i) a thermistor,
ii) a reference voltage source,
iii) an amplifier, and
iv) an amplifier feedback resistor
2. The circuit of claim 1 further comprising a linearizing resistor in series with said thermistor.
3. The circuit of claim 2 wherein the resistance of said linearizing resistor is non-zero and is selected using a numerical optimization method.
4. The circuit of claim 2 further comprising a capacitor in shunt with the thermistor
5. The circuit of claim 1 wherein said amplifier is a chopper stabilized operational amplifier.
6. The circuit of claim 1 wherein self heating of the thermistor is minimized by limiting the voltage (V) across the thermistor whose minimum resistance is RTmin such that VRTmin is less than the maximum power dissipation of the thermistor
7. The circuit of claim 6 further comprising a non-zero resistance linearization resistor
8. The circuit of claim 1 wherein the circuit is calibrated using a curve fitting method
9. A method of calibrating the circuit of claim 1 utilizing perturbation analysis in conjunction with resistors of known accuracy to correct deviations of the circuit component values from their nominal value.
10. A method in accordance with claim 9 wherein the thermistor is calibrated using a three point calibration to correct errors in the Steinhart-Hart coefficients.
11. A method of calibrating the circuit described in claim 1 wherein the thermistor calibration is achieved using a three point calibration to correct errors in the Steinhart-Hart coefficient.