1. A semiconductor device comprising:
a semiconductor substrate;
an insulated gate transistor formed to the semiconductor substrate;
a diode formed to the semiconductor substrate; and
a first control transistor formed to the semiconductor substrate,
wherein a first current terminal of the insulated gate transistor is coupled to a cathode of the diode at a high potential side,
wherein a second current terminal of the insulated gate transistor is coupled to an anode of the diode at a low potential side, and
wherein the first control transistor is configured to turn off the insulated gate transistor by reducing a potential of a gate terminal of the insulated gate transistor when the diode conducts a first electric current.
2. The semiconductor device according to claim 1, further comprising:
a first sensing resistor formed to the semiconductor substrate,
wherein the diode has a sensing anode terminal for outputting a second electric current proportional to the first electric current,
wherein the first sensing resistor is coupled between the anode and the sensing anode terminal of the diode,
wherein a control terminal of the first control transistor is coupled to the anode of the diode,
wherein the first current terminal of the first control transistor is coupled to the gate terminal of the insulated gate transistor, and
wherein the second current terminal of the first control transistor is coupled to the sensing anode terminal of the diode.
3. The semiconductor device according to claim 2, further comprising:
a second control transistor formed to the semiconductor substrate; and
a second sensing resistor formed to the semiconductor substrate,
wherein the second control transistor is configured to turn off the insulated gate transistor by reducing the potential of the gate terminal of the insulated gate transistor when a third electric current flowing through the insulated gate transistor exceeds an allowable current value,
wherein the insulated gate transistor has a sensing current terminal for outputting a fourth electric current proportional to the third electric current,
wherein the second sensing resistor is coupled between the sensing current terminal of the insulated gate transistor and the second current terminal of the insulated gate transistor,
wherein a control terminal of the second control transistor is coupled to the sensing current terminal of the insulated gate transistor,
wherein a first current terminal of the second control transistor is coupled to the gate terminal of the insulated gate transistor, and
wherein a second current terminal of the second control transistor is coupled to the second current terminal of the insulated gate transistor.
4. The semiconductor device according to claim 1, further comprising:
a first sensing resistor formed to the semiconductor substrate; and
a second sensing resistor formed to the semiconductor substrate,
wherein the diode has a sensing anode terminal for outputting a second electric current proportional to the first electric current,
wherein a third electric current flows through the insulated gate transistor,
wherein the insulate gate transistor has a sensing current terminal for outputting a fourth electric current proportional to the third electric current,
wherein the first sensing resistor is coupled between the sensing anode terminal of the diode and the sensing current terminal of the insulated gate transistor,
wherein the second sensing resistor is coupled between the sensing current terminal and the second current terminal of the insulated gate transistor,
wherein a resistance of the first sensing resistor is greater than a resistance of the second sensing resistor,
wherein a control terminal of the first control transistor is coupled to the sensing current terminal of the insulated gate transistor,
wherein the first current terminal of the first control transistor is coupled to the gate terminal of the insulated gate transistor, and
wherein the second current terminal of the first control transistor is coupled to the anode of the diode.
5. The semiconductor device according to claim 1,
wherein the insulated gate transistor is an insulated gate bipolar transistor or a vertical metal-oxide-semiconductor transistor,
wherein the first current terminal of the insulated gate transistor is a collector terminal of the insulated gate bipolar transistor or a drain terminal of the vertical metal-oxide-semiconductor transistor, and
wherein the second current terminal of the insulated gate transistor is an emitter terminal of the insulated gate bipolar transistor or a source terminal of the vertical metal-oxide-semiconductor transistor.
6. The semiconductor device according to claim 1,
wherein the first control transistor is a bipolar transistor or a metal-oxide-semiconductor,
wherein the control terminal of the first control transistor is a base terminal of the bipolar transistor or a gate terminal of the metal-oxide-semiconductor transistor,
wherein the first current terminal of the first control transistor is a collector terminal of the bipolar transistor or a drain terminal of the metal-oxide-semiconductor transistor, and
wherein the second current terminal of the first control transistor is an emitter terminal of the bipolar transistor or a source terminal of the metal-oxide-semiconductor transistor.
7. The semiconductor device according to claim 3,
wherein the second control transistor is a bipolar transistor or a metal-oxide-semiconductor transistor,
wherein the control terminal of the second control transistor is a base terminal of the bipolar transistor or a gate terminal of the metal-oxide-semiconductor transistor,
wherein the first current terminal of the second control transistor is a collector terminal of the bipolar transistor or a drain terminal of the metal-oxide-semiconductor transistor, and
wherein the second current terminal of the second control transistor is an emitter terminal of the bipolar transistor or a source terminal of the metal-oxide-semiconductor transistor.
8. The semiconductor device according to claim 1,
wherein the first control transistor is located adjacent to the insulated gate transistor or the diode.
9. The semiconductor device according to claim 3,
wherein the second control transistor is located adjacent to the insulated gate transistor or the diode.
10. The semiconductor device according to claim 1, further comprising:
an insulating trench formed to the semiconductor substrate,
wherein the first control transistor is surrounded by the insulating trench.
11. The semiconductor device according to claim 1, further comprising:
an insulating trench formed to the semiconductor substrate; and
a buried insulating layer formed to the semiconductor substrate,
wherein the first control transistor is isolated by the insulating trench and the buried insulating layer.
12. The semiconductor device according to claim 1, further comprising:
a first highly-doped layer formed to the semiconductor substrate and located directly below the first control transistor,
wherein the first highly-doped layer has the same conductivity type as the semiconductor substrate and has an impurity concentration greater than that of the semiconductor substrate.
13. The semiconductor device according to claim 1, further comprising:
a second highly-doped layer formed to the semiconductor substrate,
wherein the second highly-doped layer has the same conductivity type as the semiconductor substrate and has an impurity concentration greater than that of the semiconductor substrate,
wherein the insulated gate transistor has a trench gate structure, and
wherein the second highly-doped layer is located between a channel layer and a drift layer of the insulated gate transistor.
14. The semiconductor device according to claim 1,
wherein the semiconductor device is mounted on a vehicle.
15. An inverter circuit comprising:
a plurality of semiconductor devices, each of which is defined in claim 1.
16. The inverter circuit according to claim 15,
wherein the plurality of semiconductor devices comprises six semiconductor devices and is configured to generate a three-phase alternating current output, and
wherein the six semiconductor devices are integrated in a single semiconductor chip.
17. The inverter circuit according to claim 15,
wherein the plurality of semiconductor devices comprises six semiconductor devices and is configured to generate a three-phase alternating current output,
wherein three of the six semiconductor devices are integrated in a first single semiconductor chip, and
wherein another three of the six semiconductor devices are integrated in a second single semiconductor chip.
18. The inverter circuit according to claim 15,
wherein each of the insulated gate transistor and the diode of each of the plurality of semiconductor devices is a vertical element in which an electric current flows in a direction normal to a surface of the semiconductor substrate, and
wherein the plurality of semiconductor devices is isolated from each other by an insulating trench that penetrates through the semiconductor substrate in the direction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. An assay device comprising a plurality of detectable probes, wherein at least one of said detectable probes contains a particle that defines a hollow interior constituting from about 20% to about 100% of the spatial volume occupied by said particle.
2. An assay device as defined in claim 1, wherein said hollow interior constitutes from about 30% to about 100% of the spatial volume occupied by said particle.
3. An assay device as defined in claim 1, wherein the average size of said particle ranges from about 0.1 nanometers to about 1,000 microns.
4. An assay device as defined in claim 1, wherein the average size of said particle ranges from about 0.1 nanometers to about 100 microns.
5. An assay device as defined in claim 1, wherein the average size of said particle ranges from about 1 nanometer to about 10 microns.
6. An assay device as defined in claim 1, wherein said particle has a spherical shape.
7. An assay device as defined in claim 1, wherein said particle is formed from a polymer.
8. An assay device as defined in claim 7, wherein said particle is formed from a core polymer and a shell polymer.
9. An assay device as defined in claim 1, wherein said particle is formed by electrostatic layer deposition.
10. An assay device as defined in claim 1, wherein said at least on detectable probe further contains a label.
11. An assay device as defined in claim 1, wherein said particle is conjugated with a specific binding member.
12. An assay device as defined in claim 1, wherein the assay device is a flow-through assay device.
13. An assay device as defined in claim 1, wherein the assay device is a diffraction-based assay device.
14. A flow-through assay device for detecting an analyte in a test sample, said flow-through assay device comprising a detection zone immobilized with a receptive material, said detection zone being in fluid communication with detection probes containing particles that individually define a hollow interior constituting from about 20% to about 100% of the spatial volume occupied by said particle, wherein said detection probes are capable of generating a detection signal while within said detection zone so that the amount of the analyte within the test sample is determined from said detection signal.
15. A flow-through assay device as defined in claim 14, wherein said hollow interior constitutes from about 30% to about 100% of the spatial volume occupied by said particle.
16. A flow-through assay device as defined in claim 14, wherein said particles are conjugated with a specific binding member for the analyte.
17. A flow-through assay device as defined in claim 14, wherein said detection probes contain a label selected from the group consisting of chromogens, catalysts, fluorescent compounds, chemiluminescent compounds, phosphorescent compounds, radioactive compounds, direct visual labels, liposomes, and combinations thereof.
18. A diffraction-based assay device for detecting an analyte of interest in a test sample, said assay device comprising:
a substrate having a receptive material applied to at least one surface thereof, said receptive material being specific for the analyte;
detection probes containing particles that individually define a hollow interior constituting from about 20% to about 100% of the spatial volume occupied by said particle; and
wherein upon exposing said substrate to the test sample, the analyte is capable of binding with said receptive material on said substrate to result in a detectable diffraction pattern upon subsequent exposure of said substrate to a light source.
19. A diffraction-based assay device as defined in claim 18, wherein said hollow interior constitutes from about 30% to about 100% of the spatial volume occupied by said particle.
20. A diffraction-based assay device as defined in claim 18, wherein said substrate is selected from the group consisting of plastics, metal coated plastics and glass, functionalized plastics and glass, silicon wafers, metal oxides, glass, foils, and combinations thereof.
21. A diffraction-based assay device as defined in claim 18, wherein said substrate comprises a polymer film coated with a metal.
22. A diffraction-based assay device as defined in claim 21, wherein said metal is selected from the group consisting of gold, silver, chromium, nickel, platinum, aluminum, iron, copper, titanium, zirconium, corresponding oxides of these metals, and combinations thereof.
23. A diffraction-based assay device as defined in claim 18, wherein said receptive material is printed in a pattern on said substrate, and wherein a blocking material is further applied to non-printed areas of said substrate.
24. A detectable probe for use in an assay device, wherein the detectable probe contains a particle that defines a hollow interior constituting from about 20% to about 100% of the spatial volume occupied by said particle, said particle being conjugated with a specific binding member.
25. A detectable probe as defined in claim 24, wherein said hollow interior constitutes from about 30% to about 100% of the spatial volume occupied by said particle.
26. A detectable probe as defined in claim 24, wherein the average size of said particle ranges from about 0.1 nanometers to about 1,000 microns.
27. A detectable probe as defined in claim 24, wherein the average size of said particle ranges from about 0.1 nanometers to about 100 microns.
28. A detectable probe as defined in claim 24, wherein the average size of said particle ranges from about 1 nanometer to about 10 microns.
29. A detectable probe as defined in claim 24, wherein said particle has a spherical shape.
30. A detectable probe as defined in claim 24, wherein said particle is formed from a polymer.
31. A detectable probe as defined in claim 30, wherein said particle is formed from a core polymer and a shell polymer.
32. A detectable probe as defined in claim 24, wherein said particle is formed by electrostatic layer deposition.
33. A detectable probe as defined in claim 24, wherein said specific binding member is covalently bonded to said particle.