1. An electric machine comprising a segmented stator including a plurality of annularly arranged stator segments, each said stator segment positioned between two adjacent stator segments and defining at least one track, a plurality of end caps for supporting winding wire, an end shield, and a plurality of pins formed with the end shield, the stator segments being positioned on the end shield such that each said pin is received within a different one of said tracks, wherein the end shield and the pins are monolithically formed as a single component.
2. The machine of claim 1, wherein the pins and tracks are configured such that the engagement therebetween at least inhibits relative rotational movement between the stator segments and the end shield.
3. The machine of claim 2, wherein the pins are not threaded.
4. The machine of claim 3, wherein the end shield defines only one said pin for each said stator segment, and each said stator segment defines only one said track.
5. The machine of claim 4, wherein each track has opposite ends and wherein each pin extends beyond only one of said opposite ends.
6. The machine of claim 5, wherein each said track is formed along an outer side surface from a top to a bottom of the corresponding stator segment.
7. An electric supercharger comprising the machine of claim 6.
8. A vehicle comprising the electric supercharger of claim 7.
9. The machine of claim 1 wherein each stator segment is configured to receive only one end cap.
10. The machine of claim 1 wherein the tracks are substantially c-shaped.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A stress test method for a flash memory device having column selection transistors configured to select a predetermined bitline from among a plurality of bitlines that are coupled to flash memory cells, the stress test method comprising:
activating a plurality of column selection signals to a high voltage provided directly from an external source;
applying the plurality of column selection signals to all the column selection transistors;
deactivating all the column selection signals; and
turning on selected ones of the column selection transistors in response to a column address.
2. The stress test method of claim 1, wherein providing the high voltage directly from an external source comprises providing the high voltage with a voltage level higher than a power supply voltage.
3. The stress test method of claim 1, wherein the column selection transistors are NMOS transistors.
4. A stress test method for a flash memory device having column selection transistors configured to select a predetermined bitline from among a plurality of bitlines that are coupled to flash memory cells, the stress test method comprising:
activating a plurality of column selection signals to a high voltage;
applying the plurality of column selection signals to all the column selection transistors;
deactivating all the column selection signals;
turning on selected ones of the column selection transistors in response to a column address; and
applying a constant voltage to the plurality of bitlines.
5. The stress test method of claim 4, wherein applying a constant voltage to the plurality of bitlines comprises applying a ground voltage.
6. A flash memory device with a column predecoder, the column predecoder configured to control column selection transistors that select a predetermined bitline from among a plurality of bitlines that are coupled to flash memory cells, the column predecoder comprising:
a buffer unit configured to receive as input an all column selection signal;
decoder units configured to decode an output of the buffer unit and a column address; and
level shifters configured to generate column selection signals that are applied to gates of the column selection transistors in response to an output of the decoder units, wherein the level shifters are configured to apply a high voltage to all the column selection transistors during a stress test in response to the all column selection signal, the level shifters including
first and second PMOS transistors each having a source, a drain, and a gate, wherein the sources of the first and second PMOS transistors are coupled to a high voltage and the gates thereof are cross-coupled to the drains thereof,
an inverter configured to invert the output of the decoder unit,
a first NMOS transistor coupled between the drain of the first PMOS transistor and a ground voltage, with a gate coupled to an output of the inverter, and
a second NMOS transistor coupled between the drain of the second PMOS transistor and the ground voltage, with a gate coupled to the output of the decoder unit, and with a drain coupled to the drain of the second PMOS transistor to generate the column selection signal.
7. The flash memory device of claim 6, wherein the buffer unit comprises an inverter.
8. The flash memory device of claim 6, wherein each of the decoder units comprise a NAND gate configured to receive as input the output of the buffer unit and the column address.
9. The flash memory device of claim 6, wherein the high voltage is provided directly from an external source.
10. The flash memory device of claim 6, wherein the high voltage has a voltage level higher than a power supply voltage.
11. The flash memory device of claim 6, wherein a constant voltage level is applied to the bitline during the stress test.
12. The flash memory device of claim 11, wherein the constant voltage level is a ground voltage level.
13. A flash memory device comprising:
a column predecoder, the column predecoder configured to control column selection transistors that select a predetermined bitline from among a plurality of bitlines that are coupled to flash memory cells, the column predecoder including
a buffer unit configured to receive as input an all column selection signal,
decoder units configured to decode an output of the buffer unit and a column address, and
level shifters configured to generate column selection signals that are applied to gates of the column selection transistors in response to an output of the decoder units, wherein the level shifters are configured to apply a high voltage to all the column selection transistors during a stress test in response to the all column selection signal; and
a column decoder, the column decoder configured to divide the column selection transistors into predetermined stages, the column decoder including
first-stage column selection transistors configured to select at least two bitlines from among the plurality of bitlines in response to a group of the column selection signals, and
second-stage column selection transistors configured to select a predetermined one of the at least two bitlines in response to another group of the column selection signals and connect the predetermined one of the at least two bitlines with a data line.
14. The flash memory device of claim 13, wherein the column selection transistors are NMOS transistors.
15. The flash memory device of claim 13, wherein the buffer unit comprises an inverter.
16. The flash memory device of claim 13, wherein each of the decoder units comprise a NAND gate configured to receive as input the output of the buffer unit and the column address.
17. The flash memory device of claim 13, wherein the high voltage is provided directly from an external source.
18. The flash memory device of claim 13, wherein the high voltage has a voltage level higher than a power supply voltage.
19. The flash memory device of claim 13, wherein a constant voltage level is applied to the bitline during the stress test.
20. The flash memory device of claim 19, wherein the constant voltage level is a ground voltage level.