1. A differential transmission line comprising:
a substrate having a first surface and a second surface that are substantially parallel to each other,
a first grounding conductor disposed on the second surface of the substrate;
a dielectric layer disposed on the first grounding conductor;
a second grounding conductor disposed on the dielectric layer; and
first and the second signal conductors disposed so as to be parallel to each other on the first surface of the substrate;
wherein the first signal conductor and the first and second grounding conductors constitute a first transmission line, and the second signal conductor and the first and second grounding conductors constitute a second transmission line;
wherein a slot is disposed in the first grounding conductor so as to three-dimensionally intersect with the first and second signal conductors and to be substantially orthogonal to a longitudinal direction of the first and second signal conductors;
wherein a connecting conductor connects the first grounding conductor with the second grounding conductor;
wherein the slot is disposed so as to penetrate the first grounding conductor in a thickness direction of the first grounding conductor; and
wherein the first grounding conductor is divided into two parts so as to be completely separated apart by the slot.
2. The differential transmission line as claimed in claim 1,
wherein said slot is one of a plurality of slots formed in the first grounding conductor.
3. The differential transmission line as claimed in claim 1,
wherein the slot comprises a bend provided between the first signal conductor and the second signal conductor.
4. The differential transmission line as claimed in claim 3,
wherein the slot includes:
a first slot having a first width, the first slot being provided so as to intersect with the first signal conductor; and
a second slot having a second width different from the first width, the second slot being provided so as to intersect with the second signal conductor.
5. The differential transmission line as claimed in claim 4,
wherein a difference between the first width and the second width is set to be larger than a difference between a length of the first signal conductor and a length of the second signal conductor.
6. The differential transmission line as claimed in claim 5,
wherein said slot is one of a plurality of slots formed in the first grounding conductor.
7. The differential transmission line as claimed in claim 4,
wherein said slot is one of a plurality of slots formed in the first grounding conductor.
8. The differential transmission line as claimed in claim 3,
wherein said slot is one of a plurality of slots formed in the first grounding conductor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising a substrate, and a thin film transistor and a diode which are provided on the substrate, wherein
the diode includes
a gate electrode provided on the substrate,
a gate insulating layer provided on the gate electrode,
at least one semiconductor layer provided on the gate insulating layer, the at least one semiconductor layer including a first region, an intermediate region, and a second region,
a first electrode provided on the first region, the first electrode being electrically coupled to the first region and the gate electrode,
a second electrode provided on the second region, the second electrode being electrically coupled to the second region, and
an intermediate electrode provided in the intermediate region between the first region and the second region, the intermediate electrode being electrically coupled to the intermediate region,
the at least one semiconductor layer includes a channel region between the first region and the intermediate region which extends above the gate electrode with the gate insulating layer intervening therebetween, and a resistor region which does not extend above the gate electrode with the gate insulating layer intervening therebetween,
the resistor region is arranged between the intermediate region and the second region and is arranged such that the resistor region is not overlapped by any of the first electrode, the intermediate electrode, or the second electrode, and
when the diode is in an ON state, an electric current path is defined from the first electrode, through the intermediate electrode, and into the second electrode, the electric current path including the channel region and the resistor region.
2. The semiconductor device of claim 1, wherein
the diode further includes a conductive layer which is provided between the substrate and the gate insulating layer and which is separated from the gate electrode, and
the resistor region is arranged so as to extend above the conductive layer with the intervention of the gate insulating layer therebetween.
3. The semiconductor device of claim 1, wherein
the at least one semiconductor layer is a plurality of semiconductor layers including a first semiconductor layer which includes the first region and a second semiconductor layer which includes the second region,
the intermediate electrode couples the plurality of semiconductor layers in series, and
the plurality of semiconductor layers includes a semiconductor layer which does not extend above the gate electrode.
4. The semiconductor device of claim 1, wherein the at least one semiconductor layer includes one semiconductor layer which includes the first and second regions, the channel region, and the resistor region.
5. The semiconductor device of claim 4, wherein
the diode further includes another gate electrode provided at a position which is closer to the second electrode than the gate electrode is,
the one semiconductor layer further includes another channel region provided at a position which is closer to the second electrode than the channel region is,
the another channel region extends above the another gate electrode with the intervention of the gate insulating layer therebetween, and
the resistor region is provided between the channel region and the another channel region.
6. The semiconductor device of claim 1, wherein the at least one semiconductor layer and the semiconductor layer of the thin film transistor are defined by the same semiconductor film.
7. The semiconductor device of claim 6, wherein the at least one semiconductor layer and the semiconductor layer of the thin film transistor are defined by a microcrystalline silicon film which includes a crystalline phase and an amorphous phase.
8. The semiconductor device of claim 7, wherein a volume fraction of the amorphous phase in the microcrystalline silicon film is not less than 5% and not more than 95%.
9. The semiconductor device of claim 8, wherein the volume fraction of the amorphous phase in the microcrystalline silicon film is not less than 5% and not more than 40%.
10. The semiconductor device of claim 1, wherein the at least one semiconductor layer contains a metal oxide semiconductor.
11. The semiconductor device of claim 1, further comprising a plurality of bus lines, the bus lines including a gate bus line and a source bus line which are in a lattice arrangement on the substrate,
wherein the first electrode of the diode is electrically coupled to any one of the plurality of bus lines, the second electrode of the diode is electrically coupled to another one of the plurality of bus lines.
12. The semiconductor device of claim 1, further comprising a display region which is provided on the substrate and which includes a plurality of pixels, and a driver circuit which is provided on part of the substrate other than the display region,
wherein the driving circuit includes the thin film transistor and the diode.