1. A semiconductor integrated circuit device comprising:
(a) a first memory array area which includes a plurality of first memory cells and first data lines which are formed on a first layer and connected with said first memory cells;
(b) a second memory array area which includes a plurality of second memory cells and second data lines which are formed on said first layer and connected with said second memory cells;
(c) a sense amplifier area which includes sense amplifiers;
(d) a first connecting area located between said first memory array area and said sense amplifier area; and
(e) a second connecting area located between said second memory array area and said sense amplifier area,
wherein said semiconductor integrated circuit device further includes:
(f) first lines which are formed on a second layer different from said first layer and connected with said first data lines in said first connecting area; and
(g) second lines which are formed on said second layer and connected with said second data lines in said second connecting area,
said sense amplifiers being connected between said first lines and said second lines and adapted to amplify voltage differences between said first lines and said second lines.
2. A semiconductor integrated circuit device according to claim 1, wherein said first memory array area, said first connecting area, said sense amplifier area, said second connecting area, and said second memory array area are located to align in this order in the extending direction of said first and second data lines.
3. A semiconductor integrated circuit device according to claim 1, wherein said first memory array area, said first connecting area, said sense amplifier area, said second connecting area, and said second memory array area are areas having virtually rectangular shapes,
wherein said semiconductor integrated circuit device further includes a switch forming area which is located between said first memory array area and said first connecting area,
wherein said switch forming area includes data transfer lines (IO) and switch circuits having signal transfer paths which are connected between said first data lines and said data transfer lines, said data transfer lines being formed on said second layer to extend in a direction which intersects said first lines.
4. A semiconductor integrated circuit device according to claim 2, wherein said first and second lines are laid out over said sense amplifier area.
5. A semiconductor integrated circuit device according to claim 2, wherein at least part of said first and second lines are laid out over said sense amplifier area.
6. A semiconductor integrated circuit device according to claim 2, wherein said second layer is an upper layer relative to said first layer.
7. A semiconductor integrated circuit device according to claim 2, wherein said first and second lines are formed to extend in the extending direction of said first and second data lines.
8. A semiconductor integrated circuit device according to claim 1 further including word lines which intersect said first and second data lines at right angles, said memory cells being formed at all intersections of said first and second data lines and said word lines and each made up of a data transfer MISFET and a capacitor, with the gate electrode of said MISFET being connected to a word line.
9. A semiconductor integrated circuit device according to claim 1, wherein said first lines, second lines, first data lines and second data lines are formed by use of a Levenson’s line-and-space mask which is coated with shifters of alternately different phases.
10. A semiconductor integrated circuit device according to claim 1, wherein said first and second data lines have a virtually equal line spacing.
11. A semiconductor integrated circuit device according to claim 1, wherein said first and second lines and said first and second data lines have a line spacing which is equal to a minimum working dimension.
12. A semiconductor integrated circuit device according to claim 1, wherein said memory cells are each formed in an area having a size of 4F2 (where F denotes a minimum working dimension).
13. A semiconductor integrated circuit device comprising:
(a) first data lines which are formed to extend in a first direction on a first layer and connected with a plurality of first memory cells;
(b) second data lines which are formed to extend in the first direction on said first layer and connected with a plurality of second memory cells;
(c) first lines which are formed to extend straight in the first direction on a second layer different from said first layer and connected with said first data lines;
(d) second lines which are formed to extend straight in the first direction on said second layer and connected with said second data lines; and
(e) sense amplifiers which are connected to said first lines and said second lines and adapted to amplify voltage differences between said first lines and said second lines.
14. A semiconductor integrated circuit device according to claim 13 further including word lines which intersect said first and second data lines at right angles, said memory cells being formed at all intersections of said first and second data lines and said word lines and each made up of a data transfer MISFET and a capacitor, with the gate electrode of said MISFET being connected to a word line.
15. A semiconductor integrated circuit device according to claim 13, wherein said first lines, second lines, first data lines and second data lines are formed by use of a Levenson’s line-and-space mask which is coated with shifters of alternately different phases.
16. A semiconductor integrated circuit device according to claim 13, wherein said first and second data lines have a virtually equal line spacing.
17. A semiconductor integrated circuit device according to claim 13, wherein said first and second lines and said first and second data lines have a line spacing which is equal to a minimum working dimension.
18. A semiconductor integrated circuit device according to claim 13, wherein said memory cells are each formed in an area having a size of 4F2 (where F denotes a minimum working dimension).
19. A semiconductor integrated circuit device comprising:
(a) first data lines which are formed to extend in a first direction on a first layer and connected with a plurality of first memory cells;
(b) second data lines which are formed to extend in the first direction on said first layer and connected with a plurality of second memory cells;
(c) first lines which are formed to extend straight only in the first direction on a second layer different from said first layer and connected with said first data lines;
(d) second lines which are formed to extend straight only in the first direction on said second layer and connected with said second data lines; and
(e) sense amplifiers which are connected to said first lines and said second lines and adapted to amplify voltage differences between said first lines and said second lines, said first and second lines being laid out over said sense amplifiers.
20. A semiconductor integrated circuit device comprising:
(a) first data lines which are formed to extend in a first direction on a first layer and connected with a plurality of first memory cells;
(b) second data lines which are formed to extend in the first direction on said first layer and connected with a plurality of second memory cells;
(c) sense amplifiers which amplify voltage differences between said first data lines and said second data lines;
(d) first lines which are formed to extend in the first direction on a second layer which is an upper layer relative to said first layer, and are connected between said first data lines and said sense amplifiers;
(e) second lines which are formed to extend in the first direction on said second layer and connected between said first data lines and said sense amplifiers; and
(f) precharge lines (VBLR) adapted to feed a precharge voltage to said first and second data lines,
wherein said precharge lines are formed to extend in a second direction perpendicular to the first direction on said first layer.
21. A semiconductor integrated circuit device comprising:
(a) first data lines which are formed to extend in a first direction on a first layer and connected with a plurality of first memory cells;
(b) second data lines which are formed to extend in the first direction on said first layer and connected with a plurality of second memory cells;
(c) sense amplifiers which amplify voltage differences between said first data lines and said second data lines;
(d) first lines which are formed to extend in the first direction on a second layer which is an upper layer relative to said first layer, and are connected between said first data lines and said sense amplifiers;
(e) second lines which are formed to extend in the first direction on said second layer and connected between said second data lines and said sense amplifiers; and
(f) power lines (CSN) adapted to feed a power voltage to said sense amplifiers,
wherein said power lines are formed to extend in a second direction perpendicular to the first direction on said first layer.
22. A semiconductor integrated circuit device comprising:
(a) first data lines which are formed to extend in a first direction on a first layer and connected with a plurality of first memory cells;
(b) second data lines which are formed to extend in the first direction on said first layer and connected with a plurality of second memory cells;
(c) sense amplifiers which amplify voltage differences between said first data lines and said second data lines;
(d) first lines which are formed to extend in the first direction on a second layer which is an upper layer relative to said first layer, and are connected between said first data lines and said sense amplifiers;
(e) second lines which are formed to extend in the first direction on said second layer and connected between said second data lines and said sense amplifiers; and
(f) ground lines (CSP) which are formed to extend in a second direction perpendicular to the first direction on said first layer and adapted to feed a ground voltage to said sense amplifiers.
23. A semiconductor integrated circuit device comprising:
(a) first data lines which are formed on a first layer and connected with first memory cells;
(b) second data lines which are formed on said first layer and connected with second memory cells;
(c) sense amplifiers which amplify voltage differences between said first data lines and said second data lines;
(d) first lines which are formed on a second layer which is an upper layer relative to said first layer, and are connected between said first data lines and said sense amplifiers;
(e) second lines which are formed on said second layer and connected between said second data lines and said sense amplifiers; and
(f) voltage lines (CSP, CSN) adapted to feed voltages to said sense amplifiers,
wherein said voltage lines are formed on said first layer to extend in a direction which intersects said first lines.
24. A semiconductor integrated circuit device comprising:
(a) a first memory array area which includes a plurality of first memory cells and first data lines which are formed on a first layer and connected with said first memory cells;
(b) a second memory array area which includes a plurality of second memory cells and second data lines which are formed on said first layer and connected with said second memory cells;
(c) a sense amplifier area which includes sense amplifiers;
(d) a first connecting area located between said first memory array area and said sense amplifier area;
(e) a second connecting area located between said second memory array area and said sense amplifier area; and
(f) a switch forming area which is located between said first memory array area and said first connecting area,
wherein said semiconductor integrated circuit device further includes:
(g) first lines which are formed on a second layer different from said first layer and connected in said first connecting area to said first data lines;
(h) second lines which are formed on said second layer and connected in said second connecting area to said second data lines,
said switch forming area including data transfer lines (IO) and switch circuits having signal transfer paths which are connected between said first data lines and said data transfer lines, and
said data transfer lines being formed on said first layer to extend in a direction which intersects said first lines.
25. A semiconductor integrated circuit device comprising:
(a) a first memory array area which includes a plurality of first memory cells and first data lines which are formed on a first layer and connected with said first memory cells;
(b) a second memory array area which includes a plurality of second memory cells and second data lines which are formed on said first layer and connected with said second memory cells;
(c) a sense amplifier area which includes sense amplifiers;
(d) a first connecting area located between said first memory array area and said sense amplifier area;
(e) a second connecting area located between said second memory array area and said sense amplifier area; and
(f) a switch forming area which includes switch circuits connected between said first data lines and data transfer lines,
wherein said semiconductor integrated circuit device further includes:
(g) first lines which are formed on a second layer different from said first layer and connected in said first connecting area to said first data lines; and
(h) second lines which are formed on said second layer and connected in said second connecting area to said second data lines,
said switch forming area being formed between said sense amplifier area and said first connecting area, with lines different from said first and second lines and formed on said second layer over said switch forming area.
26. A semiconductor integrated circuit device comprising:
(a) a first memory array area which includes a plurality of first memory cells and first data lines which are formed on a first layer and connected with said first memory cells;
(b) a second memory array area which includes a plurality of second memory cells and second data lines which are formed on said first layer and connected with said second memory cells;
(c) a sense amplifier area which includes sense amplifiers;
(d) a first connecting area located between said first memory array area and said sense amplifier area;
(e) a second connecting area located between said second memory array area and said sense amplifier area;
(f) a switch forming area which includes switch circuits connected between said first data lines and data transfer lines; and
(g) a precharge circuit forming area which includes precharge circuits connected between said first data lines and said second data lines,
wherein said semiconductor integrated circuit device further includes:
(h) first lines which are formed on a second layer different from said first layer and connected in said first connecting area to said first data lines; and
(i) second lines which are formed on said second layer and connected in said second connecting area to said second data lines,
said switch forming area being formed between said sense amplifier area and said first connecting area, with lines different from said first and second lines and formed on said second layer over said switch forming area and said precharge circuit forming area.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A device for measuring sexual function comprising:
an adjustable ring forming an opening to receive a penis;
at least one diagnostic sensor positioned on an inner surface of the adjustable ring, wherein the ring automatically couples the diagnostic sensor to the penis throughout a range of ring diameters, wherein the at least one diagnostic sensor includes a temperature sensor configured to measure penile temperature data; and
a microcontroller in communication with the at least one diagnostic sensor,
wherein the at least one diagnostic sensor measures data during sexual activity and communicates the data and the penile temperature data to the microcontroller.
2. The device of claim 1 wherein at least a portion of the adjustable ring is an elastic circumferential gauge, wherein the microcontroller is configured to receive data from the elastic circumferential gauge.
3. The device of claim 1 further comprising a power supply module.
4. The device of claim 1 further comprising a wireless communication module.
5. The device of claim 1 wherein the data includes blood flow data, rigidity data, temperature data, 3-axis acceleration data, or combinations thereof.
6. The device of claim 1 wherein the at least one diagnostic sensor includes a blood flow sensor configured to measure blood flow data.
7. The device of claim 6 wherein the blood flow sensor includes an ultrasound transducer.
8. The device of claim 1 wherein the at least one diagnostic sensor includes a rigidity sensor configured to measure penile rigidity data, wherein the rigidity sensor includes an ultrasound transducer.
9. The device of claim 1 wherein the device further includes an accelerometer, wherein the microcontroller is configured to receive 3-axis acceleration data from the accelerometer.
10. The device of claim 1 wherein the device includes a pulse oximeter sensor configured to measure oxygenation data, wherein the microcontroller is configured to receive oxygenation data from the pulse oximeter sensor.
11. The device of claim 1 wherein the device further includes a strain gauge used to determine circumferential data.
12. The device of claim 1 wherein the device is configured to be worn by a user during sexual activity.
13. The device of claim 1 wherein the microcontroller adjusts the diameter of the adjustable ring based on received data.
14. A system for measuring sexual function comprising:
a device comprising:
an adjustable ring forming an opening to receive a penis, and at least one diagnostic sensor positioned on an inner surface of the adjustable ring, wherein the adjustable ring automatically couples the diagnostic sensor to the penis throughout a range of ring diameters, and wherein the at least one diagnostic sensor includes an accelerometer for monitoring movement of the penis;
a microcontroller in communication with the at least one diagnostic sensor, wherein the at least one diagnostic sensor measures data during sexual activity and communicates the data to the microcontroller; and
an application in communication with the microcontroller, wherein the application is configured to display the data received from the microcontrollers;
wherein the microcontroller is configured to receive 3-axis acceleration data from the accelerometer.
15. The system of claim 14 wherein the at least one diagnostic sensor includes a blood flow sensor including an ultrasound transducer.
16. The system of claim 14 wherein the at least one diagnostic sensor includes a rigidity sensor including an ultrasound transducer.
17. The system of claim 14 wherein the device further includes a strain gauge used to determine circumferential data.
18. The system of claim 14 wherein the microcontroller, in response to the data, is configured to adjust a diameter of the ring to enable a user to maintain an erection during sexual activity.