1. A memory device comprising:
at least one memory cell element-pair of a multi-level flash memory array, the memory cell element-pair comprising first and second elements, each element configured to store one of a blank level and two or more program levels; and
a component configured to store in the at least one memory cell element-pair a program pattern of a plurality of program pattern combinations, comprising:
two blank levels;
two program levels; and
one blank level and one program level, the levels differing by less than a predetermined value and configured to exclude from the storing, program pattern combinations having levels differing by the predetermined value or greater without replacing the excluded program pattern combinations with other combinations.
2. The memory device of claim 1, wherein the predetermined value corresponds to a maximum allowable difference between the corresponding threshold voltages of the blank level and the program level.
3. The memory device of claim 1, wherein the levels differing by less than a predetermined value corresponds to a difference between the threshold voltage of the program level of the first element and the threshold voltage of the blank level of the second element.
4. The memory device of claim 1, wherein the memory cells of the multi-level flash memory array comprise dual element nitride storage flash memory cells.
5. The memory device of claim 1, wherein the memory cells of the multi-level flash memory array comprise dual element nitride storage flash memory cells, and wherein the blank level and the two or more program levels correspond to three or more threshold voltages and three or more data states per element.
6. The memory device of claim 5, wherein the two or more program levels comprise three program levels, and wherein the predetermined value is 3, whereby the program pattern combinations comprise: 11, 22, 23, 24, 32, 33, 34, 42, 43, 44, 21, 12, 31, and 13, but exclude the 41 and 14 combinations.
7. A method of forming a memory device comprising:
forming at least one memory cell of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels; and
excluding one or more program pattern combinations that can be stored in the two or more memory elements of the at least one memory cell without replacing the excluded one or more program pattern combinations with other combinations.
8. The method of claim 7, wherein the memory cell comprises a memory cell element-pair comprising a first element and a second element, each element configured to store a blank level and two or more program levels.
9. The method of claim 8, wherein the excluding one or more program pattern combinations that can be stored in the at least one memory cell element-pair comprises restricting the program pattern combinations which may be stored to a set, comprising:
two blank levels;
two program levels; and
one blank level and one program level, wherein the difference between the corresponding threshold voltages of the blank level and the program level is less than a difference threshold voltage and excluding from the programming, pattern combinations having threshold voltages differing by the difference threshold voltage or greater without replacing the excluded one or more program pattern combinations with other combinations.
10. The method of claim 9, wherein the difference threshold voltage is a maximum allowable voltage difference between the corresponding threshold voltages of the blank level and the program level.
11. The method of claim 9, wherein the difference threshold voltage is the difference between the threshold voltage of the program level of the first element and the threshold voltage of the blank level of the second element.
12. A method of programming memory cell element-pairs of a multi-level flash memory array, each element of the element-pairs configured to store one of a blank level and two or more program levels, the method comprising:
providing two or more unprogrammed memory cell element-pairs; and
programming one or more of the memory cell element-pairs to one of a plurality of program pattern combinations, comprising:
two blank levels;
two program levels; and
one blank level and one program level, wherein the difference between the corresponding threshold voltage of the blank level and the program level is less than a difference threshold voltage and excluding from the programming, program pattern combinations having threshold voltages differing by the difference threshold voltage or greater without replacing the excluded program pattern combinations with other combinations.
13. The method of claim 12, wherein the difference threshold voltage corresponds to a maximum allowable threshold voltage difference between a first element of the element-pair from the blank level, when a second element of the element-pair is programmed to one of the two or more program levels.
14. The method of claim 12, further comprising excluding one or more of the program pattern combinations that can be stored in the at least one memory cell based on selecting only those pattern combinations that correspond to threshold voltages of the blank level and the program level that differ by less than the difference threshold voltage.
15. The method of claim 12, wherein the plurality of program patterns comprise four or more program patterns.
16. The method of claim 12, wherein the difference threshold voltage is the difference between the threshold voltage of the program level of the first element and the threshold voltage of the blank level of the second element.
17. The method of claim 12, wherein the blank level and two or more program levels correspond to three or more threshold voltages.
18. The method of claim 17, wherein the memory cells of the multi-level flash memory array comprise dual element nitride storage flash memory cells, and wherein the three or more threshold voltages correspond to three or more data states per bit or element.
19. The method of claim 12, wherein the two or more program levels comprise three program levels, and wherein the difference threshold voltage restricts the program pattern combinations to: 11, 22, 23, 24, 32, 33, 34, 42, 43, 44, 21, 12, 31, and 13, but exclude the 41 and 14 combinations.
20. The method of claim 12, wherein the two or more program levels comprise three program levels, and wherein the difference threshold voltage restricts the program pattern combinations to: 11, 22, 23, 24, 32, 33, 34, 42, 43, 44, 21, 12, but exclude the 31, 13, 41 and 14 combinations.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
joining by a first node of a network to a multicast group having a multicast address, the multicast address specified by a server using a multicast location identifier (LID) as its source lid (SLID), the first node receiving packets from the server due to the packets being sent to a unicast destination location identifier (DLID) of the first node, the server receiving reply packets from the first node having a non-multicast queue pair (OP), but a multicast DLID, where the joining is selected from the group essentially consisting of:
assigning the multicast address to the first node, such that communication to the multicast address is directed to the first node through the network, and,
mapping a multicast port on a switch of the network to a port on the first node, such that communication to the multicast address is directed to the port on the first node from the multicast port on the switch; and,
upon failure of the first node,
if the joining assigned the multicast address to the first node, joining by a second node of the network to the multicast group, such that the multicast address is assigned to the second node, and the communication to the multicast address is handled by the second node, and,
if the joining mapped the multicast port on the switch to the port on the first node, remapping the multicast port on the switch to a port on the second node, such that the communication to the multicast address is directed to the port on the second node.
2. The method of claim 1, further comprising, if the joining assigned the multicast address to the first node, prior to the second node of the network joining the multicast group, the first node leaving the multicast group by the second node sending a leave request to a subnet manager (SM) on behalf of the first node.
3. The method of claim 1, further comprising, if the joining assigned the multicast address to the first node, upon failback by the first node, assigning the multicast address to the first node, such that communication to the multicast address is again handled by the first node.
4. The method of claim 1, wherein, if the joining mapped the multicast port on the switch to the port on the first node, the multicast port on the switch is remapped to the port on the second node by the second node requesting to remap the multicast port on the switch to the second node to a subnet manager (SM), the SM remapping the multicast port on the switch to the port on the second node.
5. The method of claim 1, further comprising, if the joining mapped the multicast port on the switch to the port on the first node, upon failback by the first node, remapping the multicast port on the switch to the port on the first node, such that communication to the multicast address is again directed to the port on the first node.
6. The method of claim 1, wherein the joining by the first node of the network to the multicast group comprises the first node requesting to join the multicast group to a subnet manager (SM), the SM assigning the multicast address to the first node and mapping the multicast port on the switch to the port on the first node.
7. The method of claim 1, wherein after the joining by the first node to the multicast group, the multicast group has only a single member, the first node.
8. The method of claim 1, further comprising, upon failure of the first node, the second node initially detecting the failure of the first node.
9. A system comprising:
a server;
a first node of a subnet having a port and initially having assigned thereto in a first mode a multicast address of a multicast group, such that initially communication to the multicast address is handled by the first node, the multicast address specified by a server using a multicast location identifier (LID) as its source lid (SLID), the first node receiving packets from the server due to the packets being sent to a unicast destination location identifier (DLID) of the first node, the server receiving reply packets from the first node having a non-multicast queue pair (OP), but a multicast DLID;
a second node of the subnet having a port;
a switch of the subnet having a multicast port initially mapped in a second mode to the port on the first node; and,
a management component of the subnet where, upon failure of the first node, the management component assigns the multicast address to the second node in the first mode, and remaps the multicast port on the switch to the port on the second node in the second mode, such that communication to the multicast address is handled by the second node.
10. The system of claim 9, wherein the second node detects the failure of the first node.
11. The system of claim 9, wherein the management component detects the failure of the first node.
12. The system of claim 9, wherein upon failback by the first node, the management component assigns the multicast address to the first node in the first mode, and remaps the multicast port on the switch to the port on the first node in the second mode.
13. The system of claim 9, wherein each of the first node and the second node comprises at least one of: a host and a channel adapter (CA).
14. The system of claim 9, wherein each of the first node and the second node comprises a channel adapter (CA) on a same host.
15. The system of claim 9, wherein the network comprises a subnet having a subnet manager (SM), where the management component is the SM.
16. An article comprising:
a computer-readable medium; and,
a computer program stored in the medium and executable by a computer for performing one of two actions selected from the group essentially consisting of: assigning a multicast address of a multicast group that was initially assigned to a first node of a network that has failed to a second node of the network; and, remapping a multicast port on a switch of the network that was initially mapped to a port on the first node that has failed to a port on the second node,
wherein the multicast address is specified by a server using a multicast location identifier (LID) as its source lid (SLID), the first node receiving packets from the server due to the packets being sent to a unicast destination location identifier (DLID) of the first node, and the server receiving reply packets from the first node having a non-multicast queue pair (QP), but a multicast DLID.
17. The article of claim 16, wherein the computer program assigns the multicast address of the multicast group that was initially assigned to the first node of the network that has failed to the second node of the network in response to receiving a request from the second node to join the multicast group.
18. The article of claim 16, wherein the computer program remaps the multicast port on the switch on the network that was initially mapped to the port on the first node to the port on the second node in response to receiving a remapping request from the second node.
19. The article of claim 16, wherein the medium is a recordable data storage medium.