1. A method for reporting channel information in a wireless local area network system, the method comprising;
receiving, by a responding station, a data block for requesting a modulation and coding scheme (MCS) feedback from a requesting station, the data block including a data field and a stream indicator indicating a number of at least one spatial stream in the data field;
determining, by the responding station, the MCS feedback based on the data block; and,
transmitting, by the responding station, the MCS feedback to the requesting station, the MCS feedback including a recommended MCS and a recommended stream indicator indicating a number of at least one recommended spatial stream,
wherein the number of the at least one recommended spatial stream in the MCS feedback is equal or less than the number of the at least one spatial stream in the data block.
2. The method of claim 1,
if the number of the at least one recommended spatial stream in the MCS feedback is less than the number of the at least spatial stream in the data block,
wherein the recommended MCS is estimated under an assumption that the at least one recommended spatial stream is at least one first spatial stream among the at least one spatial stream in the data block.
3. The method of claim 2,
wherein the MCS feedback is determined based on a bandwidth used for transmitting the data field and a coding scheme applied to the data field.
4. The method of claim 3, wherein the data block further comprises;
a channel bandwidth indicator indicating the bandwidth; and, a coding scheme indicator indicating the coding scheme.
5. The method of claim 4,
wherein the data block further comprises a MRQ indicator requesting the MCS feedback.
6. The method of claim 5,
wherein the MRQ indicator is implemented 1 bit field.
7. The method of claim 6,
wherein the data block is a physical layer convergence procedure(PLCP) protocol data unit(PPDU).
8. The method of claim 7,
wherein the data field comprises a physical service data unit(PSDU), and,
wherein the MRQ indicator is included in the PSDU.
9. An wireless apparatus comprising:
a transceiver transmitting and receiving radio signal; and, a processor operationally coupled to the transceiver, wherein the processor is configured for the step of :
receiving a data block for requesting a modulation and coding scheme (MCS) feedback from a requesting station, the data block including a data field and a stream indicator indicating a number of at least one spatial stream in the data field;
determining the MCS feedback based on the data block; and, transmitting the MCS feedback to the requesting station, the MCS feedback including a recommended MCS and a recommended stream indicator indicating a number of at least one recommended spatial stream,
wherein the number of the at least one recommended spatial stream in the MCS feedback is equal or less than the number of the at least one spatial stream in the data block.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory system comprising:
a non-volatile memory device including a plurality of memory cells each of which stores data;
a monitoring unit which monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device; and
a changing unit which changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic, the writing process being a process in which a writing operation and a verification operation are alternately repeated,
wherein the memory system applies, when performing the writing operation, a first voltage to a first bit line connected to a first write memory cell, a second voltage higher than the first voltage to a second bit line connected to a second write memory cell, a third voltage higher than the second voltage to a third bit line connected to a non-write memory cell, according to a result of the verification operation, and
the changing unit changes the second voltage according to the monitored characteristic of the non-volatile memory device.
2. The memory system according to claim 1, wherein
the monitored characteristic of the non-volatile memory device includes at least one of a frequency of the writing process, a frequency of the erasing process, a time necessary for the writing process, a time necessary for the erasing process, a repeat count of the writing operation and the verification operation in the writing process, and a repeat count of an erasing operation and a verification operation in the erasing process.
3. The memory system according to claim 1, wherein
the changing unit gradually changes at least one of the value of the writing start voltage and the increase width of the writing voltage in the writing process, in accordance with the monitored characteristic of the non-volatile memory device.
4. The memory system according to claim 3,
wherein the monitoring unit determines a variation in the monitored characteristic of the non-volatile memory device step by step, and
wherein the changing unit gradually changes at least a value of an erasing start voltage in the erasing process in accordance with a result determined by the monitoring unit.
5. The memory system according to claim 1, wherein
the changing unit continuously changes at least one of the value of the writing start voltage and the increase width of the writing voltage in the writing process in accordance with the monitored characteristic of the non-volatile memory device.
6. The memory system according to claim 5, wherein
the changing unit includes:
a calculation unit which calculates a change amount of at least one of the value of the writing start voltage and the increase width of the writing voltage in accordance with the monitored characteristic of the non-volatile memory device, and
a changing processing unit which changes at least one of the value of the writing start voltage and the increase width of the writing voltage in the writing process by means of the calculated change amount.
7. The memory system according to claim 1, wherein
the changing unit changes the value of the writing start voltage in the writing process in accordance with the monitored characteristic of the non-volatile memory device.
8. The memory system according to claim 1, wherein
the changing unit changes the increase width of the writing voltage in the writing process in accordance with the monitored characteristic of the non-volatile memory device.
9. The memory system according to claim 1, wherein
the changing unit changes both the value of the writing start voltage and the increase width of the writing voltage in accordance with the monitored characteristic of the non-volatile memory device.
10. The memory system according to claim 1, wherein
the changing unit further changes a verification voltage in the writing process in accordance with the monitored characteristic of the non-volatile memory device.
11. A memory system comprising:
a non-volatile memory device including a plurality of memory cells each of which stores data;
a monitoring unit which monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device; and
a changing unit which changes at least a value of an erasing start voltage in the erasing process in accordance with the monitored characteristic,
wherein the memory system applies, when performing a writing operation in a writing process where the writing operation and a verification operation are alternately repeated, a first voltage to a first bit line connected to a first write memory cell, a second voltage higher than the first voltage to a second bit line connected to a second write memory cell, a third voltage higher than the second voltage to a third bit line connected to a non-write memory cell, according to a result of the verification operation, and
the changing unit changes the second voltage according to the monitored characteristic of the non-volatile memory device.
12. The memory system according to claim 11, wherein
the changing unit gradually changes at least the value of the erasing start voltage in the erasing process in accordance with the monitored characteristic of the non-volatile memory device.
13. The memory system according to claim 12,
wherein the monitoring unit determines a variation in the monitored characteristic of the non-volatile memory device, and
wherein the changing unit gradually changes at least the value of the erasing start voltage in the erasing process, based on a result determined by the monitoring unit.
14. The memory system according to claim 11, wherein
the changing unit changes both the value of the erasing start voltage and the increase width of the erasing voltage in the erasing process in accordance with the monitored characteristic of the non-volatile memory device.
15. A memory system comprising:
a non-volatile memory device including a plurality of memory cells each of which stores data;
a monitoring unit which monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device; and
a changing unit which changes a type of verification operation in the writing process from a first type of verification operation to a second type of verification operation in accordance with the monitored characteristic, the writing process being a process in which a writing operation and a verification operation are alternately repeated, the first type of verification operation being a operation where a verification is performed at a second verification voltage, the second type of verification operation being a operation where a verification is performed in two steps at a first verification voltage and at the second verification voltage, the first verification voltage being lower than the second verification voltage,
wherein the memory system applies, when performing the writing operation, a first voltage to a first bit line connected to a first write memory cell, a second voltage higher than the first voltage to a second bit line connected to a second write memory cell, a third voltage higher than the second voltage to a third bit line connected to a non-write memory cell, according to a result of the verification operation, and
the changing unit changes the second voltage according to the monitored characteristic of the non-volatile memory device.
16. The memory system according to claim 15, wherein
the changing unit changes at least one of a level of the first verification voltage and a charging voltage of a bit line in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device.
17. The memory system according to claim 16, wherein
the changing unit gradually changes at least one of the level of the first verification voltage and the charging voltage of the bit line in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device.
18. The memory system according to claim 16, wherein
the changing unit changes the level of the first verification voltage in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device.
19. The memory system according to claim 16, wherein
the changing unit changes the charging voltage of the bit line in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device.
20. The memory system according to claim 16, wherein
the changing unit changes both the level of the first verification voltage and the charging voltage of the bit line in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device.