What is claimed is:
1. An image processing apparatus which performs an image process to image information including condition information representing a condition at a time when an image is obtained, comprising:
analysis means for analyzing the condition information; and
processing determination means for obtaining a color correction amount of the image according to a value representing a level of color balance, a lightness correction amount of the image according to a value representing a level of lightness and a smoothing correction amount of the image according to a value concerning zoom, on the basis of an analysis result of said analysis means.
2. An image processing apparatus according to claim 1, further comprising output means for outputting the image information which has been processed by said processing means.
3. An image processing apparatus according to claim 2, wherein said output means includes a print output function.
4. An image processing apparatus according to claim 1, wherein
in the process to obtain the color correction amount of the image, lightness of a highlight point of an original image and lightness of a shadow point thereof are detected, and colors of the highlight point and the shadow point are obtained from plural pixels having said lightness, and
the color correction process is performed to the original image based on the highlight point, the shadow point and the colors of these points.
5. An image processing apparatus according to claim 4, wherein, in the color correction process, a color solid axis of the original image is conformed to an axis indicating the lightness, and contrast adjustment is performed to color components representing the lightness of the original image.
6. An image processing apparatus according to claim 4, wherein, in the color correction process, the correction process is performed to color components representing the color of the original image, thereby adjusting saturation of the original image.
7. An image processing apparatus according to claim 4, wherein a histogram is created based on color components representing the lightness of the original image, and
the highlight point and the shadow point are detected based on said histogram.
8. An image processing apparatus according to claim 1, wherein said processing determination means for obtaining the lightness correction amount of the image judges a distribution of the lightness of the image from a histogram concerning the number of pixels of values of components concerning the lightness of the image represented by image data, automatically selects one of plural gradation correction conditions based on a judged distribution, and corrects the components concerning the lightness by using the selected gradation correction condition.
9. An image processing apparatus according to claim 8, wherein the distribution of the lightness of the image is judged based on an accumulated frequency in a predetermined range of the histogram.
10. An image processing apparatus according to claim 9, wherein the distribution of the lightness of the image is judged based on a rate of the accumulated frequency in said predetermined range to the number of total pixels of the histogram.
11. An image processing apparatus according to claim 8, wherein the gradation correction condition is selected based on a combination of highlight and shadow points of the image and the distribution of the lightness of the image.
12. An image processing apparatus according to claim 8, wherein a density is increased if a rate of a highlight range on the histogram is high, the density is decreased if a rate of a shadow range on the histogram is low, and a dynamic range is expanded if a histogram width is narrow.
13. An image processing apparatus according to claim 12, wherein
in a case where the rate of the highlight range is high, a level of increase of the density is made higher as compared with a case where the rate of the highlight range is low,
in a case where the rate of the shadow range is high, a level of decrease of the density is made higher as compared with a case where the rate of the shadow range is low, and
in a case where the histogram width is small, a level of expansion of the dynamic range is made higher as compared with a case where the histogram width is large.
14. An image processing apparatus according to claim 1, wherein the image information includes image information obtained by a digital still camera.
15. An image processing apparatus according to claim 1, wherein
the image information includes shot image information, and
the condition information includes at least any of exposure information, stroboscopic information, white balance information, shooting mode information and digital zoom information at a time when the shot image information is obtained.
16. An image processing apparatus according to claim 1, further comprising presentation means for presenting information concerning the condition information.
17. An image processing apparatus according to claim 16, wherein said presentation means presents the information concerning the condition information based on processing timing of the image information to which the condition information has been added.
18. An image processing apparatus according to claim 1, wherein said analysis means includes a function to analyze the image information.
19. An image processing apparatus according to claim 1, wherein, when said processing determination means obtains the plural kinds of image information and performs the plural processes corresponding to the obtained plural kinds of image information, said processing determination means sets order of priority for each of the plural processes.
20. An image processing method which performs an image process to image information including condition information representing a condition at a time when an image is obtained, comprising:
an analysis step of analyzing the condition information; and
a processing determination step of obtaining a color correction amount of the image according to a value representing a level of color balance, a lightness correction amount of the image according to a value representing a level of lightness and a smoothing correction amount of the image according to a value concerning zoom, on the basis of an analysis result in said analysis step.
21. An image processing method which performs an image correction process to image information including condition information representing a condition at a time when an image is obtained, and performs a print process to the corrected image information, comprising:
a first analysis step of analyzing the condition information;
a second analysis step of analyzing a feature of the image information;
a first image correction condition determination step of determining the image correction condition based on an analysis result in said first analysis step;
a second image correction condition determination step of determining the image correction condition based on an analysis result in said second analysis step;
an image correction step of performing the image correction process to the image information based on the image correction conditions determined in said first and second image correction condition determination steps; and
a print step of performing the print process to the image information after processed in said image correction step.
22. An image processing method according to claim 21, further comprising an image obtaining step of obtaining the image information through shooting of a digital still camera.
23. An image processing method according to claim 21, wherein the image information includes shot image information, and
the condition information includes at least any of exposure information, stroboscopic information, white balance information and shooting mode information at a time when the shot image information is obtained.
24. A computer-readable storage medium which records a program to cause a computer to execute steps of an image processing method which performs an image process to image information including condition information representing a condition at a time when an image is obtained, said method comprising:
an analysis step of analyzing the condition information; and
a processing determination step of obtaining a color correction amount of the image according to a value representing a level of color balance, a lightness correction amount of the image according to a value representing a level of lightness and a smoothing correction amount of the image according to a value concerning zoom, on the basis of an analysis result in said analysis step.
25. A program to cause a computer to execute steps of an image processing method which performs an image process to image information including condition information representing a condition at a time when an image is obtained, said method comprising:
an analysis step of analyzing the condition information; and
a processing determination step of obtaining a color correction amount of the image according to a value representing a level of color balance, a lightness correction amount of the image according to a value representing a level of lightness and a smoothing correction amount of the image according to a value concerning zoom, on the basis of an analysis result of said analysis means.
26. An image processing method which can perform plural image processes, wherein a process for the plural image processes is performed based on restrictions according to shooting condition data at a time when an image is shot.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory device comprising:
at least one cell storing a binary data item and including a semiconductor substrate region and first, second, third and fourth active zones that are mutually laterally isolated within the substrate;
the first active zone to be connected to a first voltage, the second active zone, of an opposite type of conductivity to that of the first active zone, to be connected to a second voltage;
an electrically conductive connection adjacent the substrate and connecting together the third and fourth active zones;
a semiconductor electrical connection within the substrate to electrically connect at least one of the third and fourth active zones to at least one of the first active zone and the second active zone, depending on the logic value of the binary data item; and
a semiconductor electrical isolation within the substrate to electrically isolate the third and fourth active zones from at least one of the second active zone and the first active zone, respectively.
2. The memory device according to claim 1, wherein the semiconductor electrical isolation comprises pn junctions defining non-conducting diodes between at least one active zone and the substrate region.
3. The memory device according to claim 1, further comprising a semiconductor well located in the substrate and having an opposite type of conductivity to that of the substrate, and having an interface with at least one active zone; wherein the semiconductor electrical isolation comprises at least one pn junction defining a non-conducting diode between at least one of the at least one active zone and the semiconductor well and between the well and the substrate; and wherein the semiconductor electrical connection is defined by at least one of the substrate and the well.
4. The memory device according to claim 3, wherein the third and fourth active zones have respectively opposite types of conductivity; and wherein the well includes interfaces with the third and fourth active zones and with that of the first or second active zones having the same type of conductivity as that of the well depending on the logic value of the binary data item.
5. The memory device according to claim 3 wherein the semiconductor electrical isolation comprises pn junctions formed between the substrate and the active zones having an opposite type of conductivity to that of the substrate, or between the substrate and the semiconductor well having interfaces with the third and fourth active zones and with that of the first or second active zones having the same type of conductivity as that of the well.
6. The memory device according to claim 5 wherein the first active zone has n-type conductivity and the second active zone has p-type conductivity, and the well has n-type conductivity.
7. The memory device according to claim 3, wherein the third and fourth active zones have the same type of conductivity, the well has an interface with the third active zone and with that of the first or second active zones having the same type of conductivity as that of the well, and the type of conductivity of the third and fourth active zones is based upon the logic value of the binary data item.
8. The memory device according to claim 1, further comprising a semiconductor well located in the substrate and having an opposite type of conductivity to that of the substrate, and having an interface with at least one active zone; wherein the third and fourth active zones have the same type of conductivity, the well has an interface with the third active zone and with that of the first or second active zones having the same type of conductivity as that of the well, and the semiconductor electrical isolation comprises a pn junction forming a non-conducting diode between the well and the substrate and a pn junction forming a non-conducting diode between the third active zone and the well or between the fourth active zone and the substrate region based upon the logic value of the binary data item; and wherein the semiconductor electrical connection is defined by at least one of the substrate and the well.
9. The memory device according to claim 8, wherein that the first active zone has n-type conductivity and the second active zone has p-type conductivity, and the well has an n-type conductivity and the type of conductivity of the third and fourth active zones is based upon the logic value of the binary data item.
10. The memory device according to claim 1, wherein the first voltage is a supply voltage and the second voltage is ground.
11. The memory device according to claim 1, wherein the at least one cell comprises a plurality of cells storing a set of binary data items.
12. The memory device according to claim 1, a reading circuit for reading each cell and comprising a first voltage source connected to the first active zone, a second voltage source connected to the second active zone, and a measurement unit for measuring the voltage present at the electrically conductive connection.
13. A method for reading the logic value of a binary data item contained in a cell of a memory device, the cell including
a semiconductor substrate region and first, second, third and fourth active zones that are mutually laterally isolated within the substrate,
the first active zone to be connected to a first voltage, the second active zone, of an opposite type of conductivity to that of the first active zone, to be connected to a second voltage,
an electrically conductive connection adjacent the substrate and connecting together the third and fourth active zones,
a semiconductor electrical connection within the substrate to electrically connect at least one of the third and fourth active zones to at least one of the first active zone and the second active zone, depending on the logic value of the binary data item, and
a semiconductor electrical isolation within the substrate to electrically isolate the third and fourth active zones from at least one of the second active zone and the first active zone, respectively;
the method comprising:
applying the first voltage to the first active zone;
applying the second voltage to the second active zone; and
measuring the voltage at the electrically conductive connection.
14. A method of programming a binary data item in at least one cell comprising, within a semiconductor substrate, four active zones that are mutually laterally isolated, the first active zone to be connected to a first voltage, the second active zone, of an opposite type of conductivity to that of the first active zone, to be connected to a second voltage, the third and fourth active zones being connected together via an electrically conductive connection adjacent the substrate, the method comprising defining the value of the binary data item by an implantation in at least one of a part of the substrate and in the third and fourth active zones.
15. The method according to claim 14, wherein the third and fourth active zones have opposite types of conductivity and the logic value of the binary data is defined based upon implantation, in the substrate region, of a semiconductor well having an opposite type of conductivity to that of the substrate region, and having interfaces with the third and fourth active zones and with that of the first or second active zones having the same type of conductivity as that of the well.
16. The method according to claim 15, wherein the first active zone has the n-type conductivity and the second active zone has the p-type conductivity, and the well has n-type conductivity.
17. The method according to claim 14, wherein the third and fourth active zones both have the same type of conductivity; further comprising implanting a semiconductor well in the substrate and having an opposite type of conductivity to that of the substrate, and having an interface with the third active zone and with that of the first or second active zones having the same type of conductivity as that of the well; and wherein the logic value of the binary data item is defined based upon the type of implantation for the third and fourth active zones.
18. The method according to claim 17, wherein the first active zone has the n-type conductivity and the second active zone has the p-type conductivity, and the well has an n-type conductivity and the type of conductivity of the third and fourth active zones is of the n-type or p-type depending on the logic value of the binary data item.
19. The method according to claim 15 wherein the at least one cell comprises a plurality of cells which are programmed with values of a set of binary data items.
20. The method according to claim 19 wherein implantation of the wells comprises:
using an implantation mask having apertures defining locations of the wells; and
simultaneously implanting the wells through the apertures in the implantation mask.
21. The method according to claim 20 wherein an implantation mask of n+ type and an implantation mask of p+ type are defined; and wherein the active zones of cells are simultaneously implanted through the apertures in the implantation masks using the implantation masks in succession.
22. The method according. to claim 21, wherein the locations of the apertures in the implantation masks are defined by at least one of photolithography and an electron beam.