1. A power regulator circuit comprising:
first and second power regulators respectively configured and arranged to provide regulated power at main and standby power levels, the standby power level being less than half of the main power level; and
a controller configured and arranged to
in a standby mode, output a standby signal to operate the second power regulator for supplying power to an integrated circuit at the standby power level,
in a startup mode, output a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and output a start signal for operating a processor in the integrated circuit in a low-frequency mode via the second power regulator, and
after the start-up period, operating the first power regulator for supplying power at the main power level for operating the processor in a high-frequency mode.
2. The circuit of claim 1, wherein, in the startup mode,
the controller is configured to output a signal for operating an oscillator to power the processor in the low-frequency mode, and
the second power regulator is configured to provide regulated power to the oscillator at a startup power level.
3. The circuit of claim 1, wherein, in the startup mode,
the controller is configured to output a signal for operating an oscillator to power the processor in the low-frequency mode,
the second power regulator is configured to provide the regulated power to the oscillator for operating the oscillator at low frequency to power the processor in the low-frequency mode, and
the controller is configured to, in response to the first power regulator providing a threshold power level, control the first power regulator to provide the regulated power to the oscillator for operating the oscillator at a high frequency to power the processor in a high-frequency mode.
4. The circuit of claim 1, wherein the controller is configured and arranged to monitor the power level of the first power regulator and, in response to the first power regulator providing power at a power threshold, terminate the startup mode by turning the second power regulator off and controlling the first power regulator for supplying the power for operating the processor in the high-frequency mode.
5. The circuit of claim 1, wherein the controller is configured and arranged to output the startup signal to control the first power regulator for entering the startup mode from the standby mode in response to receiving a request for accessing the integrated circuit.
6. The circuit of claim 1, wherein the controller is configured and arranged to, in response to receiving a request for accessing the integrated circuit,
output a control signal to control the second power regulator for supplying power to the integrated circuit, and output the start signal for operating the processor in the low-frequency mode to serve the request, and
after the request has been served, output the standby signal to operate the second power regulator for supplying power to the integrated circuit at the standby power level, and outputting a control signal for turning the processor off.
7. The circuit of claim 1, wherein the controller is configured and arranged to, in the startup mode, operate the second power regulator for supplying power to the integrated circuit at a startup power level that is higher than the standby power level.
8. The circuit of claim 1, wherein the second power regulator is configured and arranged for supplying power to the integrated circuit in the startup mode at a power level that is higher than the standby power level, to operate the processor in the low-frequency mode.
9. The circuit of claim 1, wherein the controller is configured to output a control signal to power off a plurality of circuits in the integrated circuit for entering the standby mode, and to control at least one circuit in the integrated circuit to operate at the standby power level.
10. The circuit of claim 1, wherein the controller is configured to output the standby and startup signals by outputting a status signal indicative of the respective standby and startup modes.
11. The circuit of claim 1, wherein the controller is configured to output the start signal for operating a processor in the integrated circuit in a low-frequency mode by outputting a signal to operate a clock generation circuit to oscillate at low frequency for operating the processor.
12. A method for powering an integrated circuit having first and second power regulators respectively configured and arranged to provide regulated power at main and standby power levels, the standby power level being less than half of the main power level, the method comprising:
in a standby mode, outputting a standby signal to operate the second power regulator for supplying power to an integrated circuit at the standby power level,
in a startup mode, outputting a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and outputting a start signal for operating a processor in the integrated circuit in a low-frequency mode via the second power regulator, and
after the start-up period, operating the first power regulator for supplying power for operating the processor in a high-frequency mode.
13. The method of claim 12, wherein outputting a start signal for operating a processor in the integrated circuit in a low-frequency mode includes outputting a start signal for operating an oscillator to power the processor in the low-frequency mode.
14. The method of claim 12, wherein
outputting a start signal for operating a processor in the integrated circuit in a low-frequency mode includes outputting a signal for operating an oscillator to power the processor in the low-frequency mode,
continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period includes operating the second power regulator to provide the regulated power to the oscillator for operating the oscillator at low frequency to power the processor in the low-frequency mode, and
operating the first power regulator for supplying power for operating the processor in a high-frequency mode includes outputting, in response to the first power regulator providing a threshold power level, a control signal to control the first power regulator to provide the regulated power to the oscillator for operating the oscillator at a high frequency to power the processor in a high-frequency mode.
15. The method of claim 12, further including
in the startup mode, monitoring the power level of the first power regulator, and
outputting a control signal to turn the second power regulator off in response to the monitored power level of the first power regulator reaching a power threshold.
16. The method of claim 12, further including,
in response to receiving a request for accessing the integrated circuit, outputting the standby signal to control the second power regulator for supplying power to the integrated circuit, and outputting the start signal for operating the processor in the low-frequency mode to serve the request, and
after the request has been served, outputting the standby signal to operate the second power regulator for supplying power to the integrated circuit at the standby power level, and outputting a signal for turning the processor off.
17. The method of claim 12 wherein, in the startup mode, continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period includes operating the processor at a startup power level that is higher than the standby power level.
18. The method of claim 12, wherein outputting a start signal for operating a processor in the integrated circuit in a low-frequency mode via the second power regulator includes outputting a signal to operate a clock generation circuit to oscillate at low frequency for operating the processor.
19. The method of claim 12, wherein outputting a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and outputting a start signal for operating a processor in the integrated circuit include outputting the signals and operating the second power regulator in response to receiving a request for accessing the integrated circuit.
20. An integrated circuit chip comprising:
a plurality of functional circuit blocks;
a clock generation circuit configured to generate a clock signal;
a microprocessor circuit coupled to receive the clock signal and configured to operate at a frequency based upon the received clock signal;
first and second power regulators respectively configured and arranged to provide regulated power at main and standby power levels, the standby power level being less than half of the main power level; and
a power control circuit configured and arranged to
enter a standby mode in which the integrated circuit chip is not serving requests, by outputting a standby signal to operate the second power regulator for supplying power to the circuit at the standby power level,
in response to a request for accessing the integrated circuit chip, enter a startup mode by outputting a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and outputting a start signal for operating the microprocessor circuit in a low-frequency mode via the second power regulator, and
in response to the first power regulator reaching a full power level, enter a main operation mode by operating the first power regulator for supplying power at the main power level for operating the microprocessor in a high-frequency mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic apparatus comprising:
a first display device comprising a first housing and a first display screen which is held in the first housing;
a second display device comprising a second housing and a second display screen which is held in the second housing, the second display screen comprising a sensor which generates a sensor output signal depending on an input on the second display screen;
a connecting mechanism configured to connect the first and second housings together and be able to adjust an opening angle of the first housing and the second housing;
a display processing section configured to display a first display image on the first display screen and a first interface image on the second display screen;
a determining section configured to determine an instruction to the first interface image on the basis of the sensor output signal; and
a control section configured to control the display processing section in response to the instruction to display a second display image in place of the first display image on the first display screen and display a second interface image in place of the first interface image on the second display screen,
wherein the connecting mechanism sets the opening angle of the first housing and the second housing so that the first and second display screens can be viewed from one side of the electronic apparatus, and the second display screen is switched between display of the second interface image on the first interface image and non-display of the second interface image on the first interface image, the display of the second interface image on the first interface image being displayed on top of the first interface image as a translucent or opaque image.
2. The electronic apparatus according to claim 1, wherein the connecting mechanism sets the opening angle of the first housing and the second housing so that the first and second display screens can be viewed from opposite sides of the electronic apparatus, and the first and second display screens display the second display image and the second interface image corresponding to substantially the same image or the second display image and second interface image which are in a mirrored relationship.
3. The electronic apparatus according to claim 1, wherein the first display device further comprises a light source incorporated into the first housing to illuminate the first display screen, and the first housing comprises a structure configured to guide illumination light from the light source to the second display device as backlight illumination or a front-light illumination.
4. The electronic apparatus according to claim 1, wherein the first and second display screens forms one flexible and bendable display unit.
5. An electronic apparatus comprising:
a first display device comprising a first housing and a first display screen which is held in the first housing;
a second display device comprising a second housing and a second display screen which is held in the second housing, the second display screen comprising a sensor which generates a sensor output signal depending on an input on the second display screen;
a connecting mechanism configured to connect the first and second housings together and be able to adjust an opening angle of the first housing and the second housing;
a display processing section configured to display a first display image on the first display screen and a first interface image on the second display screen;
a determining section configured to determine an instruction to the first interface image on the basis of the sensor output signal; and
a control section configured to control the display processing section in response to the instruction to display a second display image in place of the first display image on the first display screen and display a second interface image in place of the first interface image on the second display screen,
wherein the first display device further comprises a light source incorporated into the first housing to illuminate the first display screen, and the first housing comprises a structure configured to guide illumination light from the light source to the second display device as backlight illumination or a front-light illumination.