1. A wafer boat for holding a plurality of semiconductor wafers in a spaced apart relationship during processing, comprising at least one support member defining a plurality of sets of at least two vertically spaced apart wafer holding provisions, each of which wafer holding provisions is configured to independently hold a wafer in a substantially horizontal orientation, and wherein said sets are arranged such that the wafer boat is configured to accommodate a plurality of juxtaposed stacks of substantially horizontally oriented, vertically spaced apart wafers.
2. The wafer boat according to claim 1, wherein said plurality of sets of wafer holding provisions includes at least three such sets, such that the wafer boat is configured to accommodate at least three juxtaposed stacks of wafers.
3. The wafer boat according to claim 1, further comprising a first end member at a lower extremity of the wafer boat and a second end member at an upper extremity of the wafer boat,
wherein said at least one support member includes a plurality of rod-shaped support members, each interconnecting said end members and defining a plurality of vertically spaced apart wafer engagement provisions,
wherein each set of wafer holding provisions is defined by a set of at least two rod-shaped support members, and wherein each individual holding provision of a certain set of wafer holding provisions is defined by at least two wafer engagement provisions defined by the rod-shaped support members defining the respective set of wafer holding provisions.
4. The wafer boat according to claim 3, wherein said wafer engagement provisions are formed by recesses in said rod-shaped support members.
5. The wafer boat according to claim 3, wherein the rod-shaped support members are substantially straight and extend in parallel between the end members, such that the wafer boat is configured to accommodate a plurality of straight, parallel stacks.
6. The wafer boat according to claim 3, wherein each set of wafer holding provisions is defined by a set of at least three rod-shaped support members.
7. The wafer boat according to claim 3, wherein at least two sets of rod-shaped support members have at least one rod-shaped support member in common.
8. The wafer boat according to claim 3, wherein at least two sets of rod-shaped support members have no rod-shaped support member in common.
9. The wafer boat according to claim 1, wherein each set of wafer holding provisions is associated with a wafer transfer direction along which wafers are insertable into and removable from the wafer holding provisions of the respective set, and
wherein said plurality of sets of wafer holding provisions includes at least two sets whose respective wafer transfer directions include an angle <90\xb0.
10. The wafer boat according to claim 9, wherein said plurality of sets of wafer holding provisions includes at least three sets of which any two respective wafer transfer directions include an angle <120\xb0.
11. The wafer boat according to claim 1, wherein each of said wafer holding provisions is configured to hold a semiconductor wafer having a characteristic main surface dimension d\u2266200 mm, and preferably d\u2266150 mm.
12. A semiconductor processing apparatus, in particular a vertical furnace, comprising a wafer boat according to claim 1.
13. The semiconductor processing apparatus according to claim 12, comprising:
a reactor tube;
a pedestal, supporting the wafer boat, and configured to be at least partly insertable into the reactor tube; and
a wafer handling robot, including a multi-link articulated arm, configured to load and unload wafers into and from the wafer holding provisions of each of the sets of wafer holding provisions of the wafer boat.
14. The semiconductor processing apparatus according to claim 13, wherein the articulated arm of wafer handling robot includes at least three links.
15. The semiconductor processing apparatus according to claim 13, wherein the wafer boat is rotatably arranged around its central axis.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of making a gate-edge diode in a diode region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the diode region and the NVM region;
forming a first conductive layer on the first dielectric layer;
forming a second dielectric layer on the first conductive layer;
forming a second conductive layer over the second dielectric layer;
forming a first mask over the diode region having a first pattern, wherein the first pattern is of a plurality of fingers and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the non-volatile memory cell;
performing an etch through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region; and
performing an implant using the gate stack and the plurality of fingers as a mask to provide sourcedrain regions adjacent to the gate stack in the NVM region and diode terminals between the fingers in the diode region to form the gate-edge diode with the diode terminals and the substrate.
2. The method of claim 1, wherein the step of forming the first mask is further characterized by the first pattern being further of a connecting bar connecting the plurality of fingers and the step of performing the etch leaves the connecting bar.
3. The method of claim 2, further comprising removing the second conductive layer from the connecting bar and leave connecting bar as a portion of the first conductive layer.
4. The method of claim 1, wherein the gate stack comprises a control gate as a portion of the second conductive layer and a floating gate as a portion of the first conductive layer.
5. The method of claim 1, further comprising forming sidewall spacers adjacent to the plurality of fingers and the gate stack.
6. The method of claim 5, wherein the step of performing the implant is further characterized by the sidewalls spacers acting as a mask.
7. The method of claim 1, further comprising removing the first dielectric layer between the fingers and adjacent to the gate stack after the step of performing the implant.
8. The method of claim 1, further comprising forming a contact to the first conductive layer.
9. The method of claim 1, further comprising forming an interlayer dielectric over the gate stack and the plurality of fingers.
10. The method of claim 9, further comprising forming contacts through the interlayer dielectric to the diode terminals.
11. A method of making a gate-edge diode in a diode region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the diode region and the NVM region;
forming a first conductive layer on the first dielectric layer;
forming a second dielectric layer on the first conductive layer;
forming a second conductive layer over the second dielectric layer;
forming a first mask over the diode region having a first pattern, wherein the first pattern is of a plurality of fingers and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of non-volatile memory cell;
performing an etch through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region;
forming sidewall spacers adjacent to the plurality of fingers and the gate stack; and
performing an implant using the gate stack, the plurality of fingers, and the sidewall spacers as a mask to provide sourcedrain regions adjacent to the gate stack in the NVM region and diode terminals between the fingers in the diode region to form the gate-edge diode with the diode terminals and the substrate.
12. The method of claim 11, wherein the step of forming the first mask is further characterized by the first pattern being further of a connecting bar connecting the plurality of fingers and the step of performing the etch leaves the connecting bar.
13. The method of claim 12, further comprising removing the second conductive layer from the connecting bar and leave connecting bar as a portion of the first conductive layer.
14. The method of claim 13, wherein the gate stack comprises a control gate as a portion of the second conductive layer and a floating gate as a portion of the first conductive layer.
15. The method of claim 14, further comprising removing the first dielectric layer between the fingers and adjacent to the gate stack after the step of performing the implant.
16. A method of making a gate-edge diode in a diode region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the diode region and the NVM region;
forming a polysilicon layer on the first dielectric layer;
forming a second dielectric layer on the polysilicon layer;
forming a conductive layer over the second dielectric layer;
forming a first mask over the diode region having a first pattern, wherein the first pattern is of a plurality of fingers and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the non-volatile memory cell;
performing an etch through the conductive layer, the second dielectric layer, and the polysilicon layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region; and
performing an implant using the gate stack and the plurality of fingers as a mask to provide sourcedrain regions adjacent to the gate stack in the NVM region and diode terminals between the fingers in the diode region to form the gate-edge diode with the diode terminals and the substrate.
17. The method of claim 16, further comprising forming sidewall spacers adjacent to the plurality of fingers and the gate stack, wherein the step of performing the implant is further characterized by the sidewalls spacers acting as a mask.
18. The method of claim 17, further comprising removing the first dielectric layer between the fingers and adjacent to the gate stack after the step of performing the implant.
19. The method of claim 18, further comprising performing a patterned etch of the polysilicon layer prior to the step of forming the conductive layer.
20. The method of claim 19, further comprising:
forming an interlayer dielectric over the gate stack and the plurality of fingers; and
forming contacts through the interlayer dielectric to the diode terminals.