We claim:
1. A method, implemented in a system, the method comprising:
receiving a block of data and a target operating system identity;
encrypting the block of data using a public key of a pair of public and private keys;
subsequently receiving a request to decrypt the encrypted block of data; and
returning the encrypted block of data to the requester only if the target operating system identity is equal to an operating system identity when the request to decrypt is received.
2. A method as recited in claim 1, wherein the pair of public and private keys are keys of a processor of the system.
3. A method as recited in claim 1, wherein the target operating system comprises a specified software identity register (SIR) value that must be current in order for the encrypted block of data to be decrypted.
4. A method comprising:
receiving a data structure to be encrypted, wherein the data structure includes content along with a statement of conditions under which the content may be decrypted; and
encrypting the content using a public key of a pair of public and private keys of a device that is to decrypt the content.
5. A method as recited in claim 4, wherein the pair of public and private keys are keys of a processor of the device.
6. A method as recited in claim 4, wherein the content comprises an arbitrary block of data.
7. A method as recited in claim 4, wherein the statement of conditions comprises a specified software identity register (SIR) value that must be current at a point of future decryption.
8. A method as recited in claim 4, wherein the statement of conditions comprises an operating system identity that an operating system executing on the device must have in order for the content to be decrypted.
9. A method as recited in claim 8, wherein the operating system identity is maintained in a software identity register (SIR).
10. A method as recited in claim 8, wherein the operating system identity is identified in a signed certificate from an operating system vendor.
11. A method as recited in claim 8, wherein the operating system identity is for an operating system that is different than an operating system executing when the data structure to be encrypted is received.
12. A method as recited in claim 4, wherein the processor that is to decrypt the content is different than a processor that encrypts the data structure.
13. One or more computer readable memories having stored thereon a plurality of instructions that, when executed by one or more processors, causes the one or more processors to:
receive a data structure to be encrypted, wherein the data structure includes content along with a statement of conditions under which the content may be decrypted; and
encrypt the content using a public key of a pair of public and private keys of a device that is to decrypt the content.
14. One or more computer readable memories as recited in claim 13, wherein the pair of public and private keys are keys of a processor of the device.
15. One or more computer readable memories as recited in claim 13, wherein the statement of conditions comprises an operating system identity that an operating system executing on the device must have in order for the content to be decrypted.
16. One or more computer readable memories as recited in claim 15, wherein the operating system identity is maintained in a software identity register (SIR).
17. One or more computer readable memories as recited in claim 15, wherein the operating system identity is identified in a signed certificate from an operating system vendor.
18. One or more computer readable memories as recited in claim 15, wherein the operating system identity is for an operating system that is different than an operating system executing when the content to be encrypted is received.
19. One or more computer readable memories as recited in claim 13, wherein the one or more processors to encrypt the content are part of a different device than the device that is to decrypt the content.
20. A system comprising:
means for receiving a data structure to be encrypted, wherein the data structure includes content along with a statement of conditions under which the content may be decrypted; and
means for encrypting the data structure using a public key of a pair of public and private keys of a processor that is to decrypt the data structure.
21. A system as recited in claim 20, wherein the statement of conditions comprises an operating system identity that an operating system executing on the processor must have in order for the data structure to be decrypted.
22. A method comprising:
decrypting a data structure using a private key of a pair of public and private keys;
obtaining a statement of conditions under which content in the data structure can be decrypted;
testing whether the conditions are satisfied; and
returning the decrypted content only if the conditions are satisfied.
23. A method as recited in claim 22, wherein the pair of public and private keys are keys of a processor.
24. A method as recited in claim 22, wherein obtaining the statement of conditions comprises obtaining the statement of conditions from the data structure.
25. A method as recited in claim 22, wherein the statement of conditions comprises an operating system identity that an operating system executing on a device including the processor must have in order for the content to be decrypted.
26. A method as recited in claim 25, wherein the operating system identity is maintained in a software identity register (SIR).
27. A method as recited in claim 25, wherein the operating system identity is identified in a signed certificate from an operating system vendor.
28. A method as recited in claim 22, further comprising returning an error if the conditions are not satisfied.
29. A method as recited in claim 22, further comprising receiving the data structure from a device other than the device that includes the processor.
30. A method as recited in claim 22, wherein the processor is different than a processor that encrypted the data structure.
31. One or more computer readable memories having stored thereon a plurality of instructions that, when executed by a processor, causes the processor to:
decrypt a data structure using a private key of a pair of public and private keys;
obtain a statement of conditions under which content in the data structure can be decrypted;
test whether the conditions are satisfied; and
return the decrypted content only if the conditions are satisfied.
32. One or more computer readable memories as recited in claim 31, wherein the pair of public and private keys are keys of the processor.
33. One or more computer readable memories as recited in claim 31, wherein the statement of conditions comprises an operating system identity that an operating system executing on a device including the processor must have in order for the content to be decrypted.
34. One or more computer readable memories as recited in claim 33, wherein the operating system identity is maintained in a software identity register (SIR).
35. One or more computer readable memories as recited in claim 33, wherein the operating system identity is identified in a signed certificate from an operating system vendor.
36. One or more computer readable memories as recited in claim 31, wherein the processor is different than a processor that encrypted the data structure
37. A system comprising:
means for decrypting a data structure using a private key of a pair of public and private keys of a processor;
means for obtaining a statement of conditions under which content in the data structure can be decrypted;
means for testing whether the conditions are satisfied; and
means for returning the decrypted content only if the conditions are satisfied.
38. A system as recited in claim 37, wherein the statement of conditions comprises an operating system identity that an operating system executing on the system must have in order for the content to be decrypted.
39. A method comprising:
obtaining a block of data to be encrypted and a target operating system identity; and
invoking a seal operation to have the block of data encrypted using a public key of a pair of public and private keys of a processor that is to be able to decrypt the block of data.
40. A method as recited in claim 39, further comprising invoking the seal operation so that only an operating system having the target operating system identity can decrypt the encrypted block of data.
41. A method as recited in claim 39, wherein the processor is different than a processor that implements the seal operation.
42. One or more computer readable memories having stored thereon a plurality of instructions that, when executed by one or more processors, causes the one or more processors to:
obtain content to be encrypted; and
invoke a seal operation, inputting both the content and a statement of conditions under which the content may be decrypted, to have the content encrypted using a public key of a pair of public and private keys of a device that may decrypt the data structure.
43. One or more computer readable memories as recited in claim 42, wherein the public and private keys are keys of a processor of the device.
44. One or more computer readable memories as recited in claim 42, wherein the statement of conditions comprises an operating system identity that an operating system executing on the device must have in order for the content to be decrypted.
45. One or more computer readable memories as recited in claim 44, wherein the operating system identity is identified in a signed certificate from an operating system vendor.
46. One or more computer readable memories as recited in claim 44, wherein the operating system identity is for an operating system that is different than an operating system invoking the seal operation.
47. One or more computer readable memories as recited in claim 42, wherein the device is a different device than a device that includes the one or more processors.
48. A method comprising:
invoking a reveal operation in order to have a data block decrypted using a private key of a pair of public and private keys of a processor; and
receiving, in response to invoking the reveal operation, the decrypted data block only if conditions under which content in the data block can be decrypted are satisfied.
49. A method as recited in claim 48, wherein the conditions comprise an operating system identity that an operating system invoking the reveal operation must have in order for the content to be decrypted.
50. A method as recited in claim 49, wherein the operating system identity of the operating system invoking the reveal operation is different than an operating system identity of an operating system that previously had the data block encrypted.
51. A method as recited in claim 48, further comprising receiving, in response to invoking the reveal operation, an error indication if the conditions are not satisfied.
52. A method as recited in claim 48, wherein the processor did not encrypt the data block.
53. One or more computer readable memories having stored thereon a plurality of instructions that, when executed by a processor, causes the processor to:
invoke a reveal operation in order to have a data block decrypted using a private key of a pair of public and private keys of the processor; and
receive, in response to invoking the reveal operation, the decrypted data block only if conditions under which content in the data block can be decrypted are satisfied.
54. One or more computer readable memories as recited in claim 53, wherein the conditions comprise an operating system identity that an operating system invoking the reveal operation must have in order for the content to be decrypted.
55. One or more computer readable memories as recited in claim 54, wherein the operating system identity of the operating system that invokes the reveal operation is different than an operating system identity of an operating system that previously had the data block encrypted.
56. One or more computer readable memories as recited in claim 53, wherein the instructions further cause the processor to receive, in response to invoking the reveal operation, an error indication if the conditions are not satisfied.
57. One or more computer readable memories as recited in claim 53, wherein the processor is a different processor than a processor that encrypted the data block.
58. One or more computer readable memories having stored thereon a plurality of instructions that, when executed by a processor of a device, causes the processor to:
make a seal operation and a reveal operation available for invoking;
wherein the seal operation causes content to be encrypted with a public key of a pair of public and private keys of the processor along with a statement of the conditions under which it may be decrypted; and
wherein the reveal operation causes the content to be returned to a requester if the conditions are satisfied.
59. One or more computer readable memories as recited in claim 58, wherein the seal operation and reveal operation collectively provide the ability to seal secrets only for subsequent use on the device.
60. One or more computer readable memories as recited in claim 58, wherein the statement of conditions comprises an operating system identity that an operating system executing on the device must have in order for the content to be decrypted.
61. One or more computer readable memories as recited in claim 60, wherein the operating system identity is identified in a signed certificate from an operating system vendor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A radio frequency transceiver for transmitting and receiving radio frequency signals, said transceiver comprising a transmitter circuit, a receiver circuit and a local oscillator circuit:
said transmitter circuit that is coupled to a transceiver reference signal for transmitting quadrature related radio frequency signals, said transmitter circuit including (a) input means for receiving an input signal that is representative of information to be modulated and for producing an intermediate signal, (b) comparator means for receiving said intermediate signal and a comparator reference signal, and for producing a comparator output signal responsive to said intermediate signal and said comparator reference signal, and (c) feedback circuitry coupled to said comparator output signal for producing a feedback signal that is coupled to said input means, said feedback circuitry including a feedback mixer that is coupled to a feedback reference signal having a frequency of about 1350 MHz;
said receiver circuit for receiving quadrature related radio frequency signals and being coupled to said transceiver reference signal; and
said local oscillator circuit for producing said transceiver reference signal for said transmitter circuit and said receiver circuit.
2. The transceiver as claimed in claim 1, wherein said input means includes a pair of quadrature related mixers and a bandpass filter.
3. The transceiver as claimed in claim 1, wherein said modulation means includes a pair of frequency dividers, a phase comparator coupled to the frequency dividers, a lowpass filter, and a pair of voltage controlled oscillators.
4. The transceiver as claimed in claim 3, wherein said modulation means further includes a bandpass filter that is coupled to one of said frequency dividers.
5. The transceiver as claimed in claim 1, wherein said feedback means includes a mixer and a bandpass filter.
6. The transceiver as claimed in claim 1, wherein said feedback means includes a mixer and a frequency divider.
7. A radio frequency transceiver for transmitting and receiving radio frequency signals having a frequency FRF, said transceiver comprising a transmitter circuit, a receiver circuit and a local oscillator circuit:
said transmitter circuit for transmitting quadrature related radio frequency signals, said transmitter circuit including frequency multiplication means for providing a 1x frequency multiplication of a local oscillator signal;
said receiver circuit for receiving quadrature related radio frequency signals and being coupled to said local oscillator signal; and
said local oscillator circuit for producing said local oscillator signal for said transmitter circuit and for said receiver circuit, said local oscillator signal having a frequency FLO where FRFFLO(1×1) in a first frequency band of operation of said transceiver, and FRFFLO(1×1) in a second frequency band of operation of said transceiver.
8. The transceiver as claimed in claim 7, wherein said frequency multiplication means includes a phase comparator that is coupled to a divide by two frequency divider and a divide by six frequency divider, the divide by six frequency divider being also coupled to said local oscillator circuit.
9. The transceiver as claimed in claim 7, wherein said frequency multiplication means includes a divide by six frequency divider that is coupled to said local oscillator circuit and to a quadrature mixer of an input unit to said transmitter circuit.
10. The transceiver as claimed in claim 1, wherein said local oscillator circuit provides a local oscillator signal having a frequency of about 1350 MHz.
11. The transceiver as claimed in claim 1, wherein said local oscillator circuit provides a local oscillator signal having a frequency of about 2.7 GHz.
12. A dual band radio frequency transceiver for transmitting and receiving dual band radio frequency signals, said transceiver comprising:
a transmitter circuit for transmitting quadrature related radio frequency signals having a frequency of FRF, said transmitter circuit including a frequency multiplication means providing a 1x frequency multiplication; and
a local oscillator circuit for providing a local oscillator signal at a frequency of FLO, where FRFFLO(1×1) in a first operation frequency band, and FRFFLO(1×1) in a second operation frequency band.
13. The transceiver as claimed in claim 12, where said transceiver further includes a receiver circuit that is coupled to said local oscillator signal.
14. The transceiver as claimed in claim 12, wherein said local oscillator signal is provided at 1350 MHz.
15. The transceiver as claimed in claim 12, wherein said local oscillator signal is provided at 2.7 GHz.
16. The transceiver as claimed in claim 12, wherein said value x equals 3.
17. The transceiver as claimed in claim 12, wherein said value x is an integer.
18. The transceiver as claimed in claim 12, wherein said dual band radio frequency signals are at 900 MHz and 1800 MHz.