1. A trench gate field effect transistor, comprising:
a trench extending into a semiconductor region;
a conductive electrode disposed in the trench, the conductive electrode being insulated from the semiconductor region by a dielectric layer, the conductive electrode including a conductive liner lining the dielectric layer along opposite sidewalls of the trench, the conductive liner having tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode, the conductive electrode further including a conductive fill material filling a center portion of the trench and sandwiched by the conductive liner;
a drift region of a first conductivity type in the semiconductor region;
a body region of a second conductivity type extending over the drift region; and
source regions of the first conductivity type in the body region adjacent the trench.
2. The field effect transistor of claim 1 wherein both the conductive liner and the conductive fill material comprise polysilicon.
3. The field effect transistor of claim 1 wherein the conductive liner comprises polysilicon and the conductive fill material comprises metal-containing material.
4. The field effect transistor of claim 1 wherein the conductive electrode is a gate electrode and the dielectric layer is a gate dielectric layer.
5. The field effect transistor of claim 4 wherein the trench further includes a thick bottom dielectric extending along the bottom of the trench directly below the gate electrode.
6. The field effect transistor of claim 1 wherein the conductive liner is discontinuous along a bottom of the conductive electrode so that the conductive liner comprises discrete conductive spacers extending over the dielectric layer along opposite sidewalls of the trench.
7. The field effect transistor of claim 1 wherein the conductive liner extending along opposite sidewalls of the trench is continuous along a bottom of the conductive electrode.
8. The field effect transistor of claim 1 wherein the conductive electrode is a shield electrode disposed in a lower portion of the trench, and the dielectric layer is a shield dielectric layer lining lower trench sidewalls.
9. The field effect transistor of claim 8 further comprising:
a gate dielectric layer lining upper trench sidewalls, the shield dielectric layer being thicker than the gate dielectric layer;
a gate electrode disposed in the trench over the shield electrode; and
inter-electrode dielectric layer extending laterally between the gate and shield electrodes.
10. The field effect transistor of claim 9 wherein the gate electrode comprises:
a conductive liner lining the gate dielectric layer, the conductive liner of the gate electrode having tapered edges such that a thickness of the conductive liner of the gate electrode gradually increases from a top surface of the gate electrode to a point in lower half of the gate electrode, and
a conductive fill material sandwiched by the conductive liner of the gate electrode.
11. The field effect transistor of claim 1 wherein the top surface of the conductive electrode is non-planar.
12. A field effect transistor, comprising:
a semiconductor region comprising a drift region of a first conductivity type and a body region of a second conductivity type extending over the drift region;
a gate electrode insulated from the body region by a gate dielectric layer;
source regions of the first conductivity type in the body region; and
a heavy body recess extending in the body region, the heavy body recess comprising:
a conductive liner lining opposite sidewalls of the heavy body recess, the conductive liner having tapered edges such that a thickness of the conductive liner gradually increases from the top of the heavy body recess to a point in lower half of the heavy body recess, and
a conductive fill material filling a center portion of the heavy body recess and sandwiched by the conductive liner.
13. The field effect transistor of claim 12 wherein both the conductive liner and the conductive fill material comprise highly doped polysilicon.
14. The field effect transistor of claim 12 wherein the conductive liner comprises doped polysilicon and the conductive fill material comprises metal-containing material.
15. The field effect transistor of claim 12 wherein the gate electrode is disposed in a trench extending through the body region and into the drift region.
16. The field effect transistor of claim 12 wherein the gate electrode is a planar gate laterally extending over the semiconductor region.
17. The field effect transistor of claim 12 wherein the conductive liner is discontinuous along a bottom of the heavy body recess so that the conductive liner comprises discrete conductive spacers extending along opposite sidewalls of the heavy body recess.
18. The field effect transistor of claim 12 wherein the conductive liner extending along opposite sidewalls of the heavy body recess is continuous along a bottom of the heavy body recess.
19. The field effect transistor of claim 12 further comprising a heavy body implant region extending in the body region along a bottom of the heavy body recess, the conductive liner being in direct contact with the heavy body implant region along the bottom of the heavy body recess.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A data acquisition system which includes:
data generating and processing units, each of which includes:
a respective data source for generating data;
data processing means which are arranged to present for output a digital data word which comprises at least two bits; and are arranged for synchronous-parallel output of the digital data words in dependence on first control signals;
shift registers which are coupled to one another and each of which:
is arranged for the synchronous parallel propagation of the digital data words in dependence on second control signals; and
is coupled to one of the data generating and processing units.
2. A data acquisition system as claimed in claim 1, wherein the data processing means of one of the data generating and processing units include an analog-to-digital converter.
3. A data acquisition system as claimed in claim 1, wherein the data processing means of one of the data generating and processing units includes a register which is arranged to store the digital data words which comprise at least two bits.
4. A data acquisition system as claimed in claim 1, wherein the data processing means of one of the data generating and processing units comprise two analog-to-digital converters coupled to a respective one of the data sources, and a register which is arranged to load digital data from each time one of the analog-to-digital converters in a temporal alternation.
5. A data acquisition system as claimed in claim 1, wherein the chain of shift registers is arranged to propagate control data.
6. A data acquisition system as claimed in claim 1, wherein one of the data sources is a sensor unit.
7. A data acquisition system as claimed in claim 1, wherein one of the data sources is arranged to detect electromagnetic radiation.
8. A data acquisition system as claimed in claim 7, wherein the data sources which is arranged to detect electromagnetic radiation comprises a plurality of detection elements.
9. An X-ray apparatus which includes a data acquisition apparatus as claimed in claim 1.
10. A method for the acquisition of data, which method includes:
generating of data in a plurality of data generating and processing units by means of a respective data source;
presentation of digital data words which comprise at least two bits by means of data processing means associated with the data generating and processing units;
synchronous-parallel output of the digital data words in dependence on first control signals;
synchronous-parallel storage of the digital data words in shift registers, coupled to one another so as to form a chain, in dependence on second control signals; and
synchronous-parallel propagation of the digital data words through the chain of shift registers in dependence on the second control signals.