1. In an on-premises pager system for alerting patrons of a business that the business is ready to provide a good or service, wherein the system includes a plurality of on-premises pagers, a transmitter located at a geographic location of the business, and wherein, in response to an activation signal addressed to one of the pagers from the transmitter, the pager selectively alerts a patron holding the pager that the business is ready to provide a good or service to the patron, a method for charging the on-premises pagers comprising:
providing a charging unit that recharges batteries within the pagers, wherein the charging unit includes a plurality of stacked slots each of which holds one of the pagers during charging, and wherein each stacked slot permits access by an operator to a pager positioned in the slot without disconnection of on-premises pagers in other slots from the charging unit; and
inserting the on-premises pagers into the stacked slots and removing the on-premises pagers from the stacked slots in accordance with one or more of a first-in-first-out (FIFO) rotation; and a level of charge of the on-premises pagers.
2. In an on-premises pager system for alerting patrons of a business that the business is ready to provide a good or service, wherein the system includes a plurality of on-premises pagers, a transmitter located at a geographic location of the business, and wherein, in response to an activation signal addressed to one of the pagers from the transmitter, the pager selectively alerts a patron holding the pager that the business is ready to provide a good or service to the patron, a system for charging the on-premises pagers, comprising:
a charging unit that recharges batteries within the pagers, wherein the charging unit includes a plurality of stacked slots each of which holds one of the pagers during charging, and wherein the charging unit includes a charging rail that simultaneously connects directly to each of the pagers in the stacked slots; and
wherein each stacked slot permits access by an operator to any pager positioned in any of the slots without disconnection of on-premises pagers in other slots from the charging unit.
3. The system of claim 2 wherein
each pager includes a pair of conductors that mechanically interlock with the charging rail in the charging unit when the pager is inserted into one of the slots.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A microprocessor comprising:
a processor core;
an information acquisition unit that acquires information encrypted to be used by the processor core, from outside;
a decryption unit that decrypts the information with a symmetric key to obtain plain text; and
a controller that, after the decryption unit obtains the plain text, uses the same symmetric key to determine whether to permit or restrict further processing of the obtained plain text.
2. The microprocessor according to claim 1, wherein
the information acquisition unit acquires information encrypted with a product key used for providing the information as a product, the product key being a symmetric key, and
the controller restricts processing of the obtained plain text decrypted with the product key.
3. The microprocessor according to claim 1, wherein
the information acquisition unit acquires information encrypted with a development key used for developing the information, the development key being a symmetric key, and
the controller permits processing of the obtained plain text decrypted with the development key.
4. The microprocessor according to claim 3, further comprising a development key generator that generates the development key,
wherein the controller permits processing of the obtained plain text decrypted with the development key generated by the development key generator.
5. The microprocessor according to claim 4, wherein the information acquisition unit acquires information encrypted with a product key used for providing the information as a product, the product key being a symmetric key,
the development key generator generates a development key that indicates the same value as the product key, and
the controller restricts processing of the obtained plain text decrypted with the product key, and permits processing of the obtained plain text decrypted with the development key generated by the development key generator.
6. The microprocessor according to claim 1, further comprising:
an symmetric key storage unit that stores a product key used for providing the information as a product, and a development key used for developing the information, the product key and the development key being symmetric keys used by the decryption unit;
a key type table in which key identification information for identifying the symmetric keys stored in the symmetric key storage unit, and key type information indicating whether one of the symmetric keys is the development key or the product key, are registered, the key identification information and key type information being associated with each other,
wherein the controller determines key type information associated in the key type table with the one of the symmetric keys, and controls processing of the obtained plain text by the decryption unit based on the key type information.
7. The microprocessor according to claim 1, further comprising a symmetric key specification unit configured to specify the symmetric key used by the decryption unit,
wherein the decryption unit decrypts the information with the symmetric key specified by the symmetric key specification unit, and
the controller controls processing of the obtained plain text by the decryption unit based on the symmetric key specified by the symmetric key specification unit.
8. The microprocessor according to claim 1, wherein
the information acquisition unit acquires the information encrypted and the symmetric key,
the decryption unit decrypts the information with the symmetric key acquired by the information acquisition unit, and
the controller controls processing of the obtained plain text by the decryption unit based on the symmetric key acquired by the information acquisition unit.
9. The microprocessor according to claim 1, further comprising:
a plain text storage unit that stores the plain text obtained by the decryption unit;
an access request acquisition unit that acquires an access request to the plain text stored in the plain text storage unit; and
a request type determiner that determines a request type of the access request,
wherein the controller controls access to the plain text to be executed by the processor core based on the request type and the symmetric key.
10. The microprocessor according to claim 9, wherein the controller restricts access to the plain text when the request type determined by the request type determiner is a request type different from request types previously registered.
11. The microprocessor according to claim 9, wherein the controller controls access to the plain text based on the symmetric key when the request type determined by the request type determiner is a request type different from request types previously registered.
12. The microprocessor according to claim 9, wherein the controller prohibits access to the plain text based on the request type and the symmetric key.
13. The microprocessor according to claim 9, wherein the controller determines whether to output the plain text or to output information obtained by encrypting the plain text, based on the request type and the symmetric key.
14. The microprocessor according to claim 9, wherein the controller restricts overwriting on the plain text based on the request type and the symmetric key.
15. The microprocessor according to claim 9, wherein
the plain text storage unit is provided in an internal memory,
instruction fetch executed by the processor core is registered as the registration request type, and
the access controller restricts access when the request type determined by the request type determiner is not instruction fetch executed by the processor core.
16. The microprocessor according to claim 9, wherein
the controller restricts access to the plain text that is being executed by the processing core, based on the request type and the symmetric key.
17. The microprocessor according to claim 1, further comprising a cache memory that stores the information acquired by the information acquisition unit,
wherein the controller controls readout of the information stored in the cache memory based on the symmetric key.
18. The microprocessor according to claim 1, further comprising a secure context switch unit that administers saving and restoration of the information acquired by the information acquisition unit, the saving and restoration is executed by the processor core,
wherein the controller controls the saving and restoration of information in the context switch unit, based on the symmetric key.
19. The microprocessor according to claim 1, further comprising:
a distributed key acquisition unit that acquires a distributed key encrypted with a public key; and
a key decryption unit that decrypts the distributed key to obtain the symmetric key,
wherein the controller controls processing on the information based on the public key used when the key decryption unit obtains the symmetric key.