1. A semiconductor target for determining overlay error, if any, between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, the target comprising:
a plurality of first structures that are invariant for a plurality of first rotation angles with respect to a first center of symmetry (COS) of the first structures; and
a plurality of second structures that are invariant for a plurality of second rotation angles with respect to a second COS of the second structures,
wherein the first rotation angles differ from the second rotation angles,
wherein the first structures and the second structures are formed on different layers of the substrate or separately generated patterns on a same layer of the substrate.
2. The target of claim 1, further comprising a plurality of third structures that are invariant for a plurality of third rotation angles with respect to a third COS of the third structures, wherein the third structures, first structures, and the second structures are formed on different layers of the substrate or separately generated patterns on a same layer of the substrate
3. The target of claim 2, wherein the third rotation angles are the same as the first rotation angles.
4. A wafer comprising the target of claim 1 and further comprising a plurality of dummy structures that fill areas around the target’s first and second structures so as to substantially eliminate empty areas near the target.
5. The wafer of claim 4, wherein the dummy structures have a density that causes the dummy structures to be measured as an unpatterned area so as to reduce cross-talk in determining overlay error in the target.
6. The target of claim 1, wherein the first layer structures each have a shape that differs from a shape of each of the second layer structures.
7. The target of claim 1, wherein the first and second COS are designed to be the same when there is no significant overlay error between the first and second layer structures.
8. The target of claim 1, wherein the first and second COS are designed to have a predefined offset when there is no significant overlay error between the first and second layer structures.
9. The target of claim 1, wherein the target is formed within an active die region of a wafer.
10. A method for determining overlay error, if any, between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, the method comprising:
acquiring an image of a plurality of first structures that are designed to be invariant for a plurality of first rotation angles with respect to a first center of symmetry (COS) of the first structures and of a plurality of second structures that are designed to be invariant for a plurality of second rotation angles with respect to a second COS of the second structures, wherein the first rotation angles differ from the second rotation angles and wherein the first structures and the second structures are formed on different layers of the substrate or separately generated patterns on a same layer of the substrate;
determining the first COS of the first structures based on rotating the image by the first rotation angles and determining the second COS of the second structures based on rotating the image by the second rotation angles; and
comparing the determined first and second COS to determine whether there is an overlay error between the first and second structures that is out of specification.
11. The method of claim 10, wherein the image is defined as an unrotated image and determining the first COS comprises:
automatically placing a rotated first image of the unrotated image that has been rotated a selected one of the first rotation angles with respect to an initial first COS; and
moving the rotated first image and the unrotated image with respect to each other and different COS’s until a best correlation and final COS is found between the first structures in the unrotated image and the rotated first image, wherein the final COS is determined to be the first COS,
wherein determining the second COS comprises:
automatically placing a rotated second image of the unrotated image that has been rotated a selected one of the second rotation angles with respect to an initial second COS; and
moving the rotated second image and the unrotated image with respect to each other and different COS’s until a best correlation and final COS is found between the second structures in the unrotated image and the rotated second image, wherein the final COS is determined to be the second COS.
12. The method of claim 10, further comprising:
for each one of the first rotation angles and for the first structures, repeating the operations for automatically placing and moving and averaging the final COS’s together; and
for each one of the second rotation angles and for the second structures, repeating the operations for automatically placing and moving and averaging the final COS’s together.
13. The method of claim 10, wherein the first and second structures are sized and positioned with respect to each other so as to substantially eliminate cross-talk and overlap of the unrotated image and the rotated first and second images when determining the COS for another one of the first or second structures.
14. The method of claim 10, wherein an overlay error is determined when the first COS differs from the second COS by more than a predetermined amount.
15. The method of claim 10, further comprising:
if an overlay error is found, repairing a wafer upon which the first and second structures were formed.
16. The method of claim 10, further comprising:
filtering a plurality of device structures from the first and second image prior to determining the first and second COS’s.
17. A method of manufacturing a semiconductor target for determining overlay error, if any, between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, comprising:
forming a plurality of first structures of a target that are invariant for a plurality of first rotation angles with respect to a first center of symmetry (COS) of the first structures; and
forming a plurality of second structures the target that are invariant for a plurality of second rotation angles with respect to a second COS of the second structures,
wherein the first rotation angles differ from the second rotation angles,
wherein the first structures and the second structures are formed on different layers of the substrate or separately generated patterns on a same layer of the substrate.
18. The method of claim 17, wherein the first and second structures of the target are formed in a scribe line between active die regions of a wafer.
19. An apparatus for determining overlay error, if any, between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, the apparatus comprising:
an optical assembly for acquiring an image of a plurality of first structures that are designed to be invariant for a plurality of first rotation angles with respect to a first center of symmetry (COS) of the first structures and of a plurality of second structures that are designed to be invariant for a plurality of second rotation angles with respect to a second COS of the second structures, wherein the first rotation angles differ from the second rotation angles and wherein the first structures and the second structures are formed on different layers of the substrate or separately generated patterns on a same layer of the substrate;
at least one memory; and
at least one processor, wherein the at least one memory and processor are configured for performing the following operations:
determining the first COS of the first structures based on rotating the image by the first rotation angles and determining the second COS of the second structures based on rotating the image by the second rotation angles; and
comparing the determined first and second COS to determine whether there is an overlay error between the first and second structures that is out of specification.
20. The apparatus of claim 19, wherein the image is defined as an unrotated image and determining the first COS comprises:
automatically placing a rotated first image of the unrotated image that has been rotated a selected one of the first rotation angles with respect to an initial first COS; and
moving the rotated first image and the unrotated image with respect to each other and different COS’s until a best correlation and final COS is found between the first structures in the unrotated image and the rotated first image, wherein the final COS is determined to be the first COS,
wherein determining the second COS comprises:
automatically placing a rotated second image of the unrotated image that has been rotated a selected one of the second rotation angles with respect to an initial second COS; and
moving the rotated second image and the unrotated image with respect to each other and different COS’s until a best correlation and final COS is found between the second structures in the unrotated image and the rotated second image, wherein the final COS is determined to be the second COS.
21. The apparatus of claim 20, wherein the at least one memory and processor are further configured for performing the following operations:
for each one of the first rotation angles and for the first structures, repeating the operations for automatically placing and moving and averaging the final COS’s together; and
for each one of the second rotation angles and for the second structures, repeating the operations for automatically placing and moving and averaging the final COS’s together.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
maintaining, by a general purpose processor, a page directory and a page table within a system memory of the general purpose processor, the page directory and the page table containing therein information for translating virtual addresses to physical addresses within a physical address space of the system memory;
offloading, by the general purpose processor, virus processing of a content object to a hardware accelerator coupled to the general purpose processor by storing virus scanning parameters, including the content object and information regarding a type of the content object, to the system memory using one or more virtual addresses and indicating to the hardware accelerator that the content object is available for virus processing;
responsive to said indicating, the hardware accelerator:
translating the one or more virtual addresses to one or more corresponding physical addresses based on the page directory and the page table;
accessing the virus scanning parameters based on the one or more corresponding physical addresses;
scanning the content object for viruses by applying a plurality of virus signatures against the content object based on the type of the content object; and
returning a result of the scanning to the general purpose processor by writing the result to the system memory.
2. The method of claim 1, wherein the virtual addresses include a directory portion, a page table portion, and an offset portion, the directory portion indicates a particular page table, the page table portion indicates a particular page, and the offset portion indicates a particular entry within the particular page.
3. The method of claim 1, wherein the virtual addresses include a directory portion and an offset portion, the directory portion indicates a particular page, and the offset portion indicates a particular entry within the particular page.
4. The method of claim 1, further comprising:
caching a most recently used page directory and page table by one or more translation lookaside buffers of the hardware accelerator;
translating the one or more virtual addresses to the one or more corresponding physical addresses based on the cached page directory and page table.
5. The method of claim 1, further comprising retrieving, by the hardware accelerator, the plurality of virus signatures from an instruction memory, each virus signature of the plurality of virus signatures specifying a pattern comparison of a plurality of pattern comparisons.
6. A method comprising:
maintaining, by a general purpose processor, a page directory and a page table within a system memory of the general purpose processor, the page directory and the page table containing therein information for translating virtual addresses to physical addresses within a physical address space of the system memory;
scanning, by the general purpose processor, a content object for viruses of a first type;
offloading, by the general purpose processor, scanning of the content object for viruses of a second type to a hardware accelerator coupled to the general purpose processor by storing virus scanning parameters, including the content object and information regarding a type of the content object, to the system memory using one or more virtual addresses and indicating to the hardware accelerator that the content object is available for virus processing;
responsive to said indicating, the hardware accelerator:
translating the one or more virtual addresses to one or more corresponding physical addresses based on the page directory and the page table;
accessing the virus scanning parameters based on the one or more corresponding physical addresses;
scanning the content object for viruses of the second type by applying a plurality of virus signatures against the content object based on the type of the content object; and
returning a result of the scanning to the general purpose processor by writing the result to the system memory.
7. The method of claim 6, wherein the viruses of the first type comprise software processed viruses and the viruses of the second type comprise hardware processed viruses.
8. The method of claim 7, wherein said scanning, by the general purpose processor, the content object for viruses of a first type and said scanning the content object for viruses of a second type are performed in parallel.
9. The method of claim 7, wherein said scanning, by the general purpose processor, the content object for viruses of a first type and said scanning the data segment for viruses of a second type are performed serially.
10. The method of claim 7, further comprising:
caching a most recently used page directory and page table by one or more translation lookaside buffers of the hardware accelerator;
translating the one or more virtual addresses to corresponding one or more physical addresses based on cached page directory and page table.
11. The method of claim 7, further comprising retrieving, by the hardware accelerator, the plurality of virus signatures from an instruction memory, each virus signature of the plurality of virus signatures specifying a pattern comparison of a plurality of pattern comparisons.
12. A virus processing system, the virus processing system comprising:
an interconnect bus;
a system memory, coupled to the interconnect bus, having stored therein a page directory and a page table containing information for translating virtual addresses to physical addresses within a physical address space of the system memory;
a general purpose processor, wherein the general purpose processor is communicably coupled to the system memory, and wherein the general purpose processor is operable to store virus scanning parameters, including a content object that is to be scanned for viruses and information regarding a type of the content object, to the system memory using one or more virtual addresses; and
a virus co-processor, coupled to the system memory via the interconnect bus, wherein the virus co-processor is operable to retrieve the virus scanning parameters from the system memory using one or more physical addresses derived based on the one or more virtual addresses, the page directory and the page table and to execute one or more virus signatures against the content object based on the type of the content object.
13. The system of claim 12, wherein the virtual addresses include a directory portion, a page table portion, and an offset portion, the directory portion indicates a particular page table, the page table portion indicates a particular page, and the offset portion indicates a particular entry within the particular page.
14. The system of claim 12, wherein the virtual addresses include a directory portion and an offset portion, the directory portion indicates a particular page, and the offset portion indicates a particular entry within the particular page.
15. The system of claim 12, wherein the virus co-processor is further operable to:
cache a most recently used page directory and page table by one or more translation lookaside buffers;
translate the one or more virtual addresses to the one or more physical addresses based on the cached page directory and page table.
16. The system of claim 12, wherein the virus co-processor is further operable to retrieve the one or more virus signatures from an instruction memory, the one or more virus signatures each specifying a pattern comparison of a plurality of pattern comparisons.