What is claimed is:
1. A method of laying out a photolithography reticle for a layer of a semiconductor die, the layer having at least three patterns to be stitched in series, that is, a first end pattern, a center pattern, and a second end pattern, the method comprising the steps of:
determining the step size of the photolithography equipment;
determining whether the center pattern is oversized relative to the step size; and
if the center pattern is oversized, moving portions of the center pattern to the first end pattern and to the second end pattern.
2. The method of claim 1, wherein the patterns are patterns of a image generating device.
3. The method of claim 1, wherein the patterns are patterns of a digital micro-mirror device.
4. The method of claim 3, wherein in the center pattern represents an array of micro-mirror elements and the end patterns represent peripheral circuitry for controlling the micro-mirror elements.
5. The method of claim 1, wherein the center pattern is for array of like elements.
6. The method of claim 1, wherein the end patterns are for peripheral circuitry for controlling elements represented by the center pattern.
7. The method of claim 1, wherein the patterns are to be stitched vertically.
8. The method of claim 1, wherein the patterns are to be stitched horizontally.
9. The method of claim 1, wherein the moving step is performed such that the remaining center pattern is smaller than the portions moved to the end pattern.
10. The method of claim 1, wherein the moving step is performed such that the remaining center pattern is as small as possible given a die size and stepper field size.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An assembly for packaging electronic devices, said assembly comprising:
one or more electronic devices arranged in a coplanar orientation that defines a plane having a first side and a second side, and defines an arrangement area determined by the planar extents of the one or more electronic devices;
a first substrate electrically coupled to the first side, said first substrate formed of one of aluminum nitride (AlN), aluminum oxide (Al2O3), and silicon nitride (Si3N4), wherein said first substrate defines a first area that encompasses the arrangement area;
a first metal layer applied only to an inner surface of the first substrate, said inner surface of the first substrate characterized as oriented toward the first side, wherein the first metal layer has a thickness between one micrometer (1 um) and twenty-five micrometer (25 um), and the first metal layer is formed of a material suitable for bonding with a silver (Ag) based sintering paste;
a second substrate electrically coupled to the second side, said second substrate formed of substantially the same material with substantially the same thickness as the first substrate, wherein said second substrate defines a second area that substantially matches the first area;
a second metal layer applied only to an inner surface of the second substrate, said inner surface of the second substrate characterized as oriented toward the second side, wherein the second metal layer has a thickness of between one micrometer (1 um) and twenty-five micrometer (25 um), and the second metal layer is formed of a metal suitable for bonding with a silver (Ag) based sintering paste;
a first lead frame interposed between the one or more electronic devices and the first substrate, said first lead frame having a surface material suitable for bonding with a silver (Ag) based sintering paste, wherein said first lead frame defines a first contact portion that corresponds to the first area of the first substrate, and a first lead portion that extends beyond the first area in a first direction;
a second lead frame interposed between the one or more electronic devices and the second substrate, said second lead frame having a surface material suitable for bonding with a silver (Ag) based sintering paste, wherein said second lead frame defines a second contact portion that corresponds to the second area of the second substrate, and a second lead portion that extends beyond the second area in a second direction distinct from the first direction;
a first paste layer of silver (Ag) based sintering paste interposed between the first substrate and the first lead frame, said first paste layer configured to form an electrical connection between the first substrate and the first lead frame;
a second paste layer of silver (Ag) based sintering paste interposed between the first lead frame and the one or more electronic devices, said second paste layer configured to form an electrical connection between the first lead frame and electrodes on the first side of the one or more devices;
a third paste layer of silver (Ag) based sintering paste interposed between the second lead frame and the one or more electronic devices, said third paste layer configured to form an electrical connection between the second lead frame and electrodes on the second side of the one or more electronic devices; and
a fourth paste layer of silver (Ag) based sintering paste interposed between the second substrate and the second lead frame, said fourth paste layer configured to form an electrical connection between the second substrate and the second lead frame.
2. The assembly in accordance with claim 1, wherein the assembly is formed by arranging the one or more electronic devices, the substrates with the respective metal layers already applied, the lead frames, and the paste layers to form a stack; heating the stack to a temperature between two hundred degrees Celsius (200\xb0 C.) and three hundred degrees Celsius (300\xb0 C.), and then cooling the stack to a temperature less than one-hundred-twenty-five degrees Celsius (125\xb0 C.).
3. The assembly in accordance with claim 2, wherein the assembly is also formed by applying a force to the stack suitable to promote sintering of the paste layers when the temperature of the stack is between two hundred degrees Celsius (200\xb0 C.) and three hundred degrees Celsius (300\xb0 C.).
4. The assembly in accordance with claim 3, wherein the force generates a pressure less than thirty mega-Pascal (30 MPa).
5. The assembly in accordance with claim 1, wherein the material and thicknesses of the substrates and lead frames are selected so stress experienced by the one or more electronic devices caused by changes in temperature of the assembly are balanced from the center of the assembly, thereby eliminating the need for balancing stresses at a substrate level by applying substantially matching metal layers to both sides of the substrates.
6. The assembly in accordance with claim 1, wherein the first lead frame and the second lead frame comprise one of silver (Ag) plated copper (Cu), and silver (Ag) plated aluminum (Al), and the thickness of the first lead frame and the second lead frame is between one-hundred micrometers (100 \u03bcm or 0.1 mm) and five-hundred micrometers (500 \u03bcm or 0.5 mm).