1. A microfluicic device for reacting a plurality of different samples with a plurality of different reagents comprising:
a) a first layer;
b) a second layer;
c) a plurality of reaction cells located in said second layer;
wherein each reaction cell comprises:
i) a first chamber located in the second layer; and
ii) a second chamber located in the second layer connected to the first chamber via an interface channel;
iii) a first valve in said interface channel between said first chamber and said second chamber that, when actuated, fluidically isolates said first chamber and said second chamber from each other;
wherein each said first chamber is in fluid communication with a first fluid channel located in said second layer, each said first fluid channel is in fluid communication with a plurality of first chambers, and each said first fluid channel is in fluid communication with a corresponding fluid inlet through which solution can be introduced into said channel;
wherein each said second chamber is in fluid communication with a second fluid channel that traverses an interface between said first and second layers; and wherein a plurality of said second fluid channels are in fluid communication with a corresponding third fluid channel, and each said third fluid channel is located in said first layer and is in fluidic communication with a corresponding fluid inlet through which solution can be introduced into said channel.
2. The device of claim 1 wherein said reaction cells are formed within an elastomeric block formed from a plurality of layers bonded together and said valve is a deflectable membrane.
3. The device of claim 1 comprising a plurality of first containment valves and a plurality of second containment valves, wherein for each reaction cell
said first chamber is associated with a first containment valve that, when actuated, fluidically isolates said first chamber form a first fluid channel;
said second chamber is associated with a second containment valve that, when actuated, fluidically isolates said second chamber from a second fluid channel; and
said first and second containment valves are controlled by a common control channel.
4. A microfluidic device for reacting M number of different samples with N number of different reagents comprising:
a first layer and a second layer;
a plurality of reaction cells in the second layer, each reaction cell comprising a first chamber and a second chamber, said first chamber and said second chamber being in fluid communication through an interface channel having an interface valve associated therewith for controlling fluid communication between said first chamber and said second chamber;
a set of inlets denoted first chamber inlets, wherein each first chamber inlet is in fluid communication with a first chamber and through which solution can be introduced into said device and into said first chamber through a via connecting said first layer to said second layer; and
a set of inlets denoted second chamber inlets through which solution can be introduced into said device and into said second chamber;
wherein each said first channel inlet is in communication with said first chamber through a first channel and each said second channel inlet is in fluid communication with said second chamber through a second channel, a portion of said first channel and a portion of said second channel being oriented parallel to each other and each having a containment valve associated therewith for controlling fluid communication therethrough, wherein said valve associated with said first channel and said valve associated with said second channel are in operable communication with each other through a common containment control channel.
5. The microfluidic device of claim 4 wherein said reaction cells are formed within an elastomeric block formed from a plurality of layers bonded together and said interface valve is a deflectable membrane.
6. The microfluidic device of claim 4 wherein said containment common control channel located along a line normal to one of said first channel or said second channel.
7. The microfluidic device of claim 4 formed from polydimethylsiloxane (PDMS).
8. The microfluidic device of claim 4 that comprises at least 1000 reaction cells.
9. A microfluidic device for reacting a plurality of different samples with a plurality of different reagents comprising:
a) a first layer;
b) a second layer;
c) a plurality of reaction cells located in said second layer;
wherein each reaction cell comprises:
i) a first chamber located in the second layer;
ii) a second chamber located in the second layer connected to the first chamber via an interface channel;
iii) a first valve in said interface channel between said first chamber and said second chamber that, when actuated, fluidically isolates said first chamber and said second chamber from each other;
wherein each said first chamber is in fluid communication with a first fluid channel located in said second layer, each said first fluid channel is in fluid communication with a plurality of first chambers, and each said first fluid channel is in fluid communication with a corresponding fluid inlet through which solution can be introduced into said channel;
wherein each said second chamber is in fluid communication with a second fluid channel connecting said second chamber in said second layer with a third fluid channel in said first layer and wherein a plurality of said second fluid channels are in fluid communication with a corresponding third fluid channel, and each said third fluid channel is located in said first layer and is in fluidic communication with a corresponding fluid inlet through which solution can be introduced into said channel.
10. The device of claim 9 wherein said reaction cells are formed within an elastomeric block formed from a plurality of layers bonded together and said valve is a deflectable membrane.
11. The device of claim 9 comprising a plurality of first containment valves and a plurality of second containment valves, wherein for each reaction cell said first chamber is associated with a first containment valve that, when actuated, fluidically isolates said first chamber from a first fluid channel; said second chamber is associated with a second containment valve that, when actuated, fluidically isolates said second chamber from a second fluid channel; and said first and second containment valves are controlled by a common control channel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A process for making a polysilicon precision resistor in an integrated circuit comprising the steps of:
depositing an insulation layer on the integrated circuit;
depositing a polysilicon layer on the insulation layer;
implanting ions into the polysilicon layer to change the resistance of the polysilicon and to damage the polysilicon layer; and
controlling the annealing of the polysilicon layer to reduce temperature coefficient of the resistance of the polysilicon resistor.
2. The method of claim 1, wherein the annealing temperature ranges from approximately 800 degrees C. to 900 degrees C.
3. The method of claim 1, wherein the implant energy of the ions ranges from approximately 10 to 3.5 KeV.
4. The method of claim 1, wherein the thickness of the polysilicon layer ranges from approximately 65 nm to 75 nm.
5. The method of claim 1, wherein two or more species of ion are implanted into the polysilicon.
6. The method of claim 1, wherein boron is one of the species.
7. A method of making a resistor in an integrated circuit, the method comprising:
forming an insulation layer overlaying a substrate of the integrated circuit;
forming a polysilicon layer overlaying the insulation layer;
implanting a relatively high concentration of dopants of one or more species in a in the polysilicon layer; and
annealing the substrate for a relatively short period of time so that a substantial amount of unannealed implant damage remains in the polysilicon layer.
8. The method of claim 7, wherein forming the insulation layer further comprises:
depositing a silicon nitride layer overlaying the substrate; and
patterning the silicon nitride layer to expose local oxidation regions.
9. The method of claim 7, wherein the insulation layer is formed from silicon dioxide.
10. The method of claim 7, wherein the insulation layer is formed from silicon nitride.
11. The method of claim 7, wherein annealing the substrate, further comprises:
performing a rapid thermal annealing at relatively low temperature of approximately 800 C. to 900 C.
12. The method of claim 7, wherein implanting dopants of one or more species in the polysilicon layer includes implanting boron and fluorine ions.
13. The method of claim 7, wherein the resistor is formed to have a temperature coefficient of resistance that is less than 100 parts per million.
14. The method of claim 7, further comprising:
forming a layer of protective oxide overlaying the polysilicon layer.
15. The method of claim 7, wherein implanting dopants of one or more species in the polysilicon layer includes implanting boron ions.
16. The method of claim 8, wherein the concentration of boron ions is approximately in the range of 91015 to 1.51016.
17. A method of forming an integrated circuit comprising:
forming one or more transition regions in a substrate to isolate MOS regions from bipolar regions in the substrate;
forming a MOS device in each MOS region of the substrate;
forming a bipolar device in each bipolar region of the substrate;
forming local oxidation (LOCOS) regions adjacent the surface of the substrate;
forming at least one polysilicon layer overlaying an associated LOCOS region;
implanting a relatively high concentration of dopants of one or more species in a in the polysilicon layer; and
annealing the substrate for a relatively short period of time so that a substantial amount of unannealed implant damage remains in the polysilicon layer thereby forming a polysilicon resistor with a relatively low temperature coefficient of resistance.
18. The method of claim 17, wherein the polysilicon layer has a thickness approximately ranging between 65 nm to 75 nm.
19. The method of claim 17, wherein the polysilicon resistor has a sheet resistance ranging approximately between 725 ohmssquare to 850 ohmssquare.
20. The method of claim 17, wherein the polysilicon resistor has a temperature coefficient of resistance (TCR) approximately ranging between 20 to 100 parts per million.
21. The method of claim 17, wherein the annealing of substrate also anneals emitters of bipolar devices.
22. The method of claim 17, wherein the annealing is carried out at approximately 900 C. for 0.5 minutes.
23. The method of claim 17, further comprising:
forming buried layers in select MOS regions and select bipolar regions, wherein at least one of the buried layers has a different diffusion coefficient than the other buried layers.
24. The method of claim 23, further comprising:
forming wells of a select conductivity type between select LOCOS regions associated with the MOS devices in forming PMOS and NMOS devices, each well extending from a surface of the substrate to an associated buried layer, wherein the select LOCOS regions providing surface lateral isolation between the PMOS and NMOS devices.
25. The method of claim 24, further comprising:
forming a P-type conductivity implant under the select LOCOS regions to provide junction isolation between the PMOS and NMOS devices.
26. The method of claim 23, further comprising:
forming a sinker diffusion in each bipolar region, each sinker diffusion extending from a surface of the substrate to an associated buried layer, wherein a select LOCOS region is used to separate each sinker diffusion from the rest of an associated bipolar device formed in the bipolar region.
27. The method of claim 26, further comprising:
forming an intrinsic base in each bipolar region, the intrinsic base being separated from an associated sinker diffusion by an associated LOCOS region;
implanting a selectively implanted contact (SIC) through the intrinsic base, wherein the SIC is in contact with an associated buried layer.
28. The method of claim 17, further comprising:
forming a protective oxide layer overlaying the poysilicon layer and
pattering the protective layer to uncover contact regions of the polysilicon resistor.
29. The method of claim 28, further comprising:
forming a platinum silicide layer overlaying the contact regions.
30. The method of claim 29, wherein the platinum layer is further formed over gate, source and drain contact regions of MOS devices and collector and emitter contact regions of bipolar devices at the same time the platinum layer is formed over the contact regions.