1. Referenceless clock and data recovery circuitry, comprising:
a first timing loop including:
an oscillator to produce a plurality of first clock signals having the same frequency but differing phases in accordance with a frequency control signal;
phase interpolation circuitry to receive the first clock signals and produce an output clock signal based on the first clock signals and a phase control signal;
a transition density detector, coupled to the output clock signal and a data input signal, to produce a transition density signal indicative of the transition density of the data input signal relative to a frequency of the output clock signal;
a frequency comparator coupled to the first clock signal and the output clock signal to produce a frequency comparison signal indicative of the relative frequencies of the first clock signals and the output clock signal; and
a controller to generate the frequency control signal based on the transition density signal and the frequency comparison signal; and
a second timing loop including:
the phase interpolation circuitry;
a phase detector to receive a data input signal and the output clock signal and to produce a phase detection signal; and
a loop filter configured to produce the phase control signal by filtering the phase detection signal.
2. The clock and data recovery device of claim 1, wherein the clock circuitry comprises a multi-modulus divider.
3. The clock and data recovery device of claim 1, wherein the clock circuitry comprises:
a phase interpolator configured to receive the first clock signal and produce a second clock signal based on the phase control signal, where the second clock signal is interpolated from two phases of a plurality of phases of the first clock signal;
a prescaler configured to receive the second clock signal and produce the output clock signal by dividing the second clock signal by a value of a prescaler control signal produced by the controller.
4. The clock and data recovery device of claim 1, wherein the controller is further configured to search for a value of the frequency control signal that results in the measurements meeting lock criteria.
5. The clock and data recovery device of claim 4, wherein the controller is further configured to search by sweeping the frequency control signal through a range of values.
6. The clock and data recovery device of claim 1, further comprising:
a first counter coupled to the output clock signal and configured to produce counts of transitions of the output clock signal;
a second counter coupled to the first clock signal and configured to produce counts of transitions of the first clock signal; and
a third counter coupled to the data input signal and configured to produce counts of transitions of the data input signal, and
wherein the frequency comparison module receives the counts from the first counter and the second counter and transition density detector receives the counts from the first counter and the third counter.
7. A method for clock and data recovery without use of an externally supplied reference clock signal, comprising:
measuring a frequency comparison indicative of the relative frequencies of a VCO clock signal and an output recovered clock signal;
measuring a data transition density indicative of transition density of a data input signal relative to the frequency of the output recovered clock signal;
searching for circuit settings that allow locking the output recovered clock signal to the data input signal, where the locking is based on the measured frequency comparison and the measured data transition density; and
tracking the data input signal, where tracking the data input signal comprises adjusting the circuit settings of a digital clock and data recovery circuit generating the output recovered clock signal to track a frequency of the data input signal and is performed after the searching meets a search criterion.
8. The method of claim 7, further comprising holding the circuit settings of the digital clock and data recovery circuit, where the holding the circuit settings of the digital clock and data recovery circuit is performed after the tracking does not meet a tracking criterion.
9. A method for clock and data recovery without use of an externally supplied reference clock signal, comprising:
measuring a frequency comparison indicative of the relative frequencies of a VCO clock signal and an output recovered clock signal;
measuring a data transition density indicative of transition density of a data input signal relative to the frequency of the output recovered clock signal;
searching for circuit settings that allow locking the output recovered clock signal to the data input signal, where the locking is based on the measured frequency comparison and the measured data transition density; wherein the searching comprises
sweeping a setting through a range of values until the measured data transition density meets a criterion, with the measuring the data transition density indicative of transition density of the data input signal relative to the frequency of the output clock signal performed for each value of the setting.
10. A method for clock and data recovery without use of an externally supplied reference clock signal, comprising:
measuring a frequency comparison indicative of the relative frequencies of a VCO clock signal and an output recovered clock signal;
measuring a data transition density indicative of transition density of a data input signal relative to the frequency of the output recovered clock signal;
searching for circuit settings that allow locking the output recovered clock signal to the data input signal, where the locking is based on the measured frequency comparison and the measured data transition density; wherein the method is performed by circuitry including a clock and data recovery circuit with a prescaler and a voltage-controlled oscillator having a range control and a frequency control, and wherein the searching for circuit settings that allow locking of the digital clock and data recovery circuit to the data input signal comprises:
sweeping a prescale control through a range of prescale control values;
sweeping a range control through a range of range control values for each value of the prescale control; and
sweeping a frequency control through a range of frequency control values for each value of the range control until the measured data transition density meets a criterion.
11. A method for clock and data recovery without use of an externally supplied reference clock signal, comprising:
measuring a frequency comparison indicative of the relative frequencies of a VCO clock signal and an output recovered clock signal;
measuring a data transition density indicative of transition density of a data input signal relative to the frequency of the output recovered clock signal;
searching for circuit settings that allow locking the output recovered clock signal to the data input signal, where the locking is based on the measured frequency comparison and the measured data transition density; wherein the method is performed by circuitry including a clock and data recovery circuit with a prescaler and a voltage-controlled oscillator having a range control and a frequency control, and wherein the searching for circuit settings that allow locking of the digital clock and data recovery circuit to the data input signal comprises:
sweeping a prescale control through a range of prescale control values;
sweeping a range control through a range of range control values for each value of the prescale control; and
sweeping a frequency control through a range of frequency control values for each value of the range control until the measured data transition density and the measured frequency comparison meet criteria.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A latch circuit comprising:
a sample section activated during a sample period by a sample signal to sample a pair of complementary data signals, to deliver said complementary data signals through a pair of sample output nodes;
a latch section activated during a hold period by a hold signal to latch said complementary data signals through said sample output nodes, to deliver said complementary data signals through a pair of latch output nodes, said sample signal and said hold signal occurring alternately with each other; and
a precharge section for precharging said latch output nodes during said sample period, wherein:
said latch section includes first and second inverters for receiving said complementary data signals through said sample output nodes, and a latch-section activating circuit for activating said first and second inverters during said hold period;
said first inverter includes a first transistor having a gate connected to one of said sample output nodes and connected between a high-potential power source line and one of said latch output nodes, a second transistor connected between said one of said latch output nodes and the other of said sample output nodes and being OFF during said sample period, and a third transistor having a gate connected to the other of said latch output nodes and connected between said other of said sample output nodes and a low-potential power source line; and
said second inverter includes a fourth transistor having a gate connected to said other of said sample output nodes and connected between said high-potential power source line and said other of said latch output nodes, a fifth transistor connected between said other of said latch output nodes and said one of said sample output nodes and being OFF during said sample period, and a sixth transistor having a gate connected to said one of said latch output nodes and connected between said one of said sample output nodes and said low-potential power source line.
2. The latch circuit according to claim 1, wherein said latch-section activating circuit includes a seventh transistor connected between said third transistor and said low-potential power source line and being ON during said hold period, and an eighth transistor connected between said sixth transistor and said low-potential power source line and being ON during said hold period.
3. The latch circuit according to claim 1, wherein said latch-section activating circuit includes a seventh transistor connected between a node connecting said third transistor and said sixth transistor in common and said low-potential power source line and being ON during said hold period.
4. The latch circuit according to claim 1, wherein:
said sample section includes first and second data signal input blocks;
said first data signal input block includes seventh and eighth transistors connected in series between said high-potential power source line and said one of said sample output nodes, said seventh transistor having a gate receiving one of said complementary data signals, said eighth transistor being ON during said sample period, and ninth and tenth transistors connected in series between said low-potential power source line and said one of said sample output nodes, said ninth transistor having a gate receiving the other of said complementary data signals, said tenth transistor being ON during said sample period; and
said second data signal input block includes eleventh and twelfth transistors connected in series between said high-potential power source line and said other of said sample output nodes, said eleventh transistor having a gate receiving said other of said complementary data, signals, said twelfth transistor being ON during said sample period, and thirteenth and fourteenth transistors connected in series between said low-potential power source line and said other of said sample output nodes, said thirteenth transistor having a gate receiving said one of said complementary data signals, said fourteenth transistor being ON during said sample period.
5. The latch circuit according to claim 1, wherein:
said sample section includes first and second data signal input blocks, and a sample-section activating block for activating said first and second data signal input blocks during said sample period;
said first data signal input block includes seventh transistor connected between said high-potential power source line and said one of said sample output nodes and having a gate receiving one of said complementary data signals, and an eighth transistor connected between said low-potential power source line and said one of said sample output nodes and having a gate receiving the other of said complementary data signals; and
said second data signal input block includes ninth transistor connected between said high-potential power source line and said other of said sample output nodes and having a gate receiving said other of said complementary data signals, and a tenth transistor connected between said low-potential power source line and said other of said sample output nodes and having a gate receiving said one of said complementary data signals.
6. The latch circuit according to claim 5, wherein said sample-section activating block includes an eleventh transistor connected in series with said seventh transistor between said high-potential power source line and said one of said sample output nodes and being ON during said sample period, a twelfth transistor connected in series with said eighth transistor between said low-potential power source line and said one of said sample output nodes and being ON during said sample period, a thirteenth transistor connected in series with said ninth transistor between said high-potential power source line and said other of said sample output nodes and being ON during said sample period, and a fourteenth transistor connected in series with said tenth transistor between said low-potential power source line and said other of said sample output nodes and being ON during said sample period.
7. The latch circuit according to claim 5, wherein said sample-section activating block includes an eleventh transistor connected between a node connecting said seventh transistor and said ninth transistor in common and said high-potential power source line and being ON during said sample period, and a twelfth transistor connected between a node connecting said eighth transistor and said tenth transistor in common and said low-potential power source line and being ON during said sample period.