1. A protection panel provided with a touch input function for a display window of an electronic device, the protection panel being fitted and retained with no gap in a panel fitting portion of a casing provided with an opening such that an outer surface thereof forms one plane together with a periphery, and protecting a display device disposed therebelow so as to be externally visible through a transparent window portion,
the protection panel comprising:
a protection panel main body including a plastic plate having a glass plate fitting opening punched out so as to be larger than the transparent window portion, and a glass plate fitted in the glass plate fitting opening;
a lower electrode sheet including a transparent resin film for the lower electrode sheet, a lower transparent electrode in a quadrilateral shape, and a lower circuit surrounding the lower transparent electrode, the lower transparent electrode and the lower circuit being provided on an upper surface of the transparent resin film for the lower electrode sheet, the lower electrode sheet being attached to an upper surface of the protection panel main body;
an upper electrode sheet including a transparent resin film for the upper electrode sheet, an upper transparent electrode in a quadrilateral shape, and an upper circuit surrounding the upper transparent electrode, the upper transparent electrode and the upper circuit being provided on a lower surface of the transparent resin film for the upper electrode sheet, the upper electrode sheet being bonded to the lower electrode sheet at peripheral edges thereof so as to form a gap between the lower transparent electrode and the upper transparent electrode; and
a decorative sheet including a transparent resin film for the decorative sheet, and a decorative layer that is provided on at least one surface of the transparent resin film for the decorative sheet so as to hide the lower circuit and the upper circuit and form the transparent window portion, the decorative sheet being attached to an upper surface of the upper electrode sheet.
2. The protection panel provided with a touch input function for a display window of an electronic device according to claim 1, further comprising:
an FPC connected with respective output terminals of the lower circuit and the upper circuit.
3. The protection panel provided with a touch input function for a display window of an electronic device according to claim 1, wherein the plastic plate has through holes.
4. A method for manufacturing a protection panel for a display window of an electronic device, the protection panel being fitted and retained with no gap in a panel fitting portion of a casing provided with an opening such that an outer surface thereof forms one plane together with a periphery, and protecting a display device disposed therebelow so as to be externally visible through a transparent window portion,
the method comprising:
forming a collective protection panel main body including a plastic plate having a plurality of glass plate fitting openings punched out so as to be larger than the transparent window portion, and glass plates respectively fitted in the glass plate fitting openings;
forming a collective lower electrode sheet including a plurality of lower transparent electrodes in a quadrilateral shape, and a plurality of lower circuits arranged respectively at peripheries of the lower transparent electrodes, the lower transparent electrodes and the lower circuits being provided on an upper surface of a transparent resin film for the collective lower electrode sheet;
forming a collective upper electrode sheet including a plurality of upper transparent electrodes in a quadrilateral shape, and a plurality of upper circuits arranged respectively at peripheries of the upper transparent electrodes, the upper transparent electrodes and the upper circuits being provided on a lower surface of a transparent resin film for the collective upper electrode sheet;
forming a collective decorative sheet including decorative layers provided on at least one surface of a transparent resin film for the collective decorative sheet so as to hide the lower circuits and the upper circuits and form the plurality of transparent window portions; and
attaching the collective lower electrode sheet on an upper surface of the collective protection panel main body, attaching the collective upper electrode sheet to the collective lower electrode sheet such that air spaces are provided between the electrodes, and attaching the collective decorative sheet on an upper surface of the collective upper electrode sheet to obtain a laminated body.
5. The protection panel provided with a touch input function for a display window of an electronic device according to claim 2, wherein the plastic plate has through holes.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device, comprising:
a first latch circuit for simultaneously latching K-bit input data (K is an integer), which is received by simultaneously pre-fetching from an internal core circuit through global inputoutput lines, in response to an input latch control signal;
a first multiplexing circuit for selecting K2-bit input data among K-bit input data in response to a first selection control signal;
a second multiplexing circuit for selecting 2-bit input data among the K2-bit input data in response to a second selection control signal; and
a second latch circuit for alternately latching the 2-bit data to sequentially output the latch data as output data in response to output latch control signals.
2. The pipe latch circuit as set forth in claim 1, wherein the first latch circuit comprises:
an even latch circuit for holding each of even-ordered bits among the K-bit input data; and
an odd latch circuit for holding each of odd-ordered bits among the K-bit input data.
3. The pipe latch circuit as set forth in claim 2, wherein the first selection control signal includes first and second selection signals; and wherein the first multiplexing circuit comprises:
a first multiplexer for outputting a half of the even-ordered input data bits in response to the first selection signal; and
a second multiplexer for outputting a half of the odd-ordered input data bits in response to the second selection signal.
4. The pipe latch circuit as set forth in claim 3, wherein the second multiplexing circuit comprises:
a third multiplexer for outputting one of output signals of the first and second multiplexers in response to the second selection control signal; and
a fourth multiplexer for outputting one of output signals of the first and second multiplexers in response to the second selection control signal,
wherein the fourth multiplexer selects the output signal of the second multiplexer while the third multiplexer selects the output signal of the first multiplexer.
5. The pipe latch circuit as set forth in claim 3, wherein logical levels of the first and second selection signals are determined by a value of one among two lower bits of a column address signal received from an external system when bits of the K-bit input data are simultaneously pre-fetched, while a logical level of the second selection control signal is determined by the other among the two lower bits.
6. The pipe latch circuit as set forth in claim 3, wherein the first and second multiplexing circuits operate in a sequential or interleaving mode in response to the first and second selection signals, and a data output order of the second latch circuit in the sequential mode is different from that in the interleaving mode.
7. The pipe latch circuit as set forth in claim 1, wherein logical levels of the first and second selection control signals are determined by values of partial lower bits of a column address signal received from an external system when bits of the K-bit input data are simultaneously pre-fetched.
8. The pipe latch circuit as set forth in claim 2, wherein the first multiplexing circuit comprises:
a first multiplexer selectively outputting a half of the even-ordered input data bits in response to the first selection control signal; and
a second multiplexer selectively outputting a half of the odd-ordered input data bits in response to the first selection control signal.
9. The pipe latch circuit as set forth in claim 8, wherein the second selection control signal includes first and second selection signals; and wherein the second multiplexing circuit comprises:
a third multiplexer selectively outputting one of output signals of the first multiplexer in response to the first selection signal;
a fourth multiplexer selectively outputting one of output signals of the second multiplexer in response to the first selection signal;
a fifth multiplexer selectively outputting one of output signals of the third and fourth multiplexers in response to the second selection signal; and
a sixth multiplexer selectively outputting the other of output signals of the third and fourth multiplexers in response to the first selection signal,
wherein the sixth multiplexer selects the output signal of the fourth multiplexer while the fifth multiplexer selects the output signal of the third multiplexer.
10. The pipe latch circuit as set forth in claim 8, wherein a logical level of the first selection control signal is determined by a value of one among third lower bits of a column address signal received from an external system when bits of the K-bit input data are simultaneously pre-fetched, a logical level of the first selection signal is determined by a value of a second one among the three lower bits, and a logical level of the second selection signal is determined by the third one of the three lower bits.