What we claim is:
1. A nonvolatile memory apparatus comprising:
a plurality of memories; and
a processing unit,
wherein each of said memories has a terminal used for data input and for data output, said terminal of each of said memories are coupled to each other by a bus,
wherein one of said memories is a nonvolatile memory and is capable of being specified a plurality of operations from said processing unit,
wherein said nonvolatile memory operates an erase operation for erasing data stored therein, said erase operation is included in said operations specified from said processing unit, and said nonvolatile memory is capable of freeing said terminal during said erase operation,
wherein said erase operation includes a threshold voltage moving operation and a verify operation,
wherein said threshold voltage moving operation is that in which a threshold voltage of a memory cell in said nonvolatile memory is moved to within a threshold voltage distribution indicative of an erase level,
wherein said verify operation determines whether the threshold voltage movement of said memory cell to within said threshold voltage distribution is completed,
wherein said nonvolatile memory repeats said erase operation when the threshold voltage movement of said memory cell to within said threshold voltage distribution is not yet completed, the erase operation of said nonvolatile memory ending when the threshold voltage of said memory cell is indicative of said erase level, and
wherein said processing unit is capable of accessing other ones of said memories via said bus during a time said erase operation is being performed in said nonvolatile memory.
2. The nonvolatile memory apparatus according to claim 1,
wherein said processing unit performs a polling to said nonvolatile memory for detecting whether said erase operation is completed or not.
3. The nonvolatile memory apparatus according to claim 2,
wherein said nonvolatile memory is enabled to operate a program operation for storing data in said nonvolatile memory, said program operation is included in said operations specified from said processing unit.
4. The nonvolatile memory apparatus according to claim 3,
wherein said threshold voltage of said memory cell is within one of a plurality of threshold voltage distributions,
wherein one of said threshold voltage distributions is indicative of said erase level, and
wherein another one of said threshold voltage distributions is indicative of a program level to which said threshold voltage of a memory cell is moved to by said program operation.
5. The nonvolatile memory apparatus according to claim 4,
wherein said nonvolatile memory comprises a plurality of memory cells and a voltage generating circuit,
wherein said voltage generating circuit is capable of generating an erase voltage and a program voltage,
wherein said voltage generating circuit supplies said erase voltage to ones of said memory cells selected for erasing data therein, and
wherein said voltage generating circuit supplies said program voltage to ones of said memory cells selected for programming data therein.
6. A nonvolatile memory apparatus comprising:
a plurality of nonvolatile memories;
a control unit; and
a bus,
wherein each of said nonvolatile memories includes a terminal used for data input and for data output, said terminal of each of said nonvolatile memories are coupled to each other by said bus, and a plurality of memory cells, each of which has a threshold voltage within one of a plurality of threshold voltage ranges,
wherein each of said nonvolatile memories operates a first operation including a threshold voltage moving operation and a verify operation,
wherein said threshold voltage moving operation is that in which said threshold voltage of a respective memory cell is moved to a first threshold voltage range in said plurality of threshold voltage ranges,
wherein said verify operation determines whether the threshold voltage moving operation of said memory cell to said first threshold voltage range is completed,
wherein said nonvolatile memory repeats said threshold voltage moving operation and said verify operation when the threshold voltage movement of that memory cell to said first threshold voltage range is not yet completed, said first operation of said nonvolatile memory ending when the threshold voltage of said memory cell is in the first threshold voltage range, and
wherein said control unit is capable of accessing other ones of said nonvolatile memories via said bus during a time said first operation is being performed in an individual nonvolatile memory.
7. The nonvolatile memory apparatus according to claim 6,
wherein said control unit performs a polling to said one nonvolatile memory for detecting whether said first operation is completed or not.
8. The nonvolatile memory apparatus according to claim 7,
wherein each of said nonvolatile memories further includes a voltage generating circuit,
wherein said voltage generating circuit is capable of generating a first voltage, and
wherein said voltage generating circuit supplies said first voltage to ones of said memory cells selected for moving the threshold voltage thereof.
9. A nonvolatile memory apparatus comprising:
a processing unit;
a plurality of nonvolatile memories; and
an inputoutput terminal,
wherein each of said nonvolatile memories has a terminal used for data input and for data output,
wherein said terminal of each of said memories and said inputoutput terminal are coupled to each other by a bus,
wherein said processing unit is capable of designating an erase operation to each of said nonvolatile memories for erasing data stored therein,
wherein said erase operation includes a threshold voltage moving operation and a verify operation,
wherein said threshold voltage moving operation is that in which a threshold voltage of a memory cell in a respective nonvolatile memory is moved to a threshold voltage range indicating an erase state,
wherein said verify operation determines whether the threshold voltage moving operation of said memory cell to said erase state is completed,
wherein said nonvolatile memory repeats said erase operation when the threshold voltage moving operation of said memory cell to that of an erase state is not yet completed, the erase operation of said nonvolatile memory ending when the threshold voltage of said memory cell is indicative of said erase state,
wherein, for selective erasure, said processing unit designates said erase operation to a first nonvolatile memory of said nonvolatile memories for performing said erase operation in said first nonvolatile memory,
wherein said first nonvolatile memory is capable of freeing said terminal when performing said erase operation and is capable of outputting a signal for indicating that said erase operation is being performed, and
wherein said processing unit is capable of inputting data from outside of said nonvolatile memory apparatus via said inputoutput terminal during a time said erase operation is being performed in said first nonvolatile memory.
10. The nonvolatile memory apparatus according to claim 9,
wherein said processing unit performs a polling to said nonvolatile memory for detecting whether said erase operation is completed or not.
11. The nonvolatile memory apparatus according to claim 10,
wherein said processing unit is capable of designating a program operation for storing data to said nonvolatile memories except when said erase operation is being performed in those memories.
12. The nonvolatile memory apparatus according to claim 11,
wherein each of said nonvolatile memories contains a plurality of memory cells and a voltage generating circuit, which is capable of generating an erase voltage and a program voltage,
wherein said voltage generating circuit supplies said erase voltage to ones of said memory cells selected for said erase operation, and
wherein said voltage generating circuit supplies said program voltage to ones of said memory cells selected for said program operation.
13. A nonvolatile memory apparatus comprising:
a processing unit;
a plurality of nonvolatile memories; and
an inputoutput terminal,
wherein each of said nonvolatile memories has a terminal used for data input and for data output,
wherein said terminal of each of said memories and said inputoutput terminal are coupled to each other by a bus,
wherein said processing unit is capable of designating an erase operation to each of said nonvolatile memories for erasing data stored therein,
wherein said erase operation includes a threshold voltage moving operation and a verify operation,
wherein said threshold voltage moving operation is that in which a threshold voltage of a memory cell in a respective nonvolatile memory is moved to a threshold voltage range indicating an erase state,
wherein said verify operation determines whether the threshold voltage moving operation of said memory cell to said erase state is completed,
wherein said nonvolatile memory repeats said erase operation when the threshold voltage moving operation of said memory cell to that of an erase state is not yet completed, the erase operation of said nonvolatile memory ending when the threshold voltage of said memory cell is indicative of said erase state,
wherein, for selective erasure, said processing unit designates said erase operation to a first nonvolatile memory of said nonvolatile memories for performing said erase operation in said first nonvolatile memory,
wherein said first nonvolatile memory is capable of freeing said terminal when performing said erase operation and is capable of outputting a signal for indicating that said erase operation is being performed, and
wherein said processing unit is capable of outputting data to outside of said nonvolatile memory apparatus via said inputoutput terminal during a time said erase operation is being performed in said first nonvolatile memory.
14. The nonvolatile memory apparatus according to claim 13,
wherein said processing unit performs a polling to said nonvolatile memory for detecting whether said erase operation is completed or not.
15. The nonvolatile memory apparatus according to claim 14,
wherein said processing unit is capable of designating a program operation for storing data to said nonvolatile memories except when said erase operation is being performed in those memories.
16. The nonvolatile memory apparatus according to claim 15,
wherein each of said nonvolatile memories contains a plurality of memory cells and a voltage generating circuit, which is capable of generating an erase voltage and a program voltage,
wherein said voltage generating circuit supplies said erase voltage to ones of said memory cells selected for said erase operation, and
wherein said voltage generating circuit supplies said program voltage to ones of said memory cells selected for said program operation.
17. A nonvolatile memory apparatus comprising:
a processing unit;
a plurality of memories; and
an inputoutput terminal,
wherein each of said memories has a terminal used for data input and for data output,
wherein said terminal of each of said memories and said inputoutput terminal are coupled to each other by a bus,
wherein at least one of said memories is a nonvolatile memory,
wherein said processing unit is capable of designating an erase operation to said nonvolatile memory for erasing data stored therein,
wherein said erase operation includes a threshold voltage moving operation and a verify operation,
wherein said threshold voltage moving operation is that in which a threshold voltage of a memory cell in a respective nonvolatile memory is moved to a threshold voltage range indicating an erase state,
wherein said verify operation determines whether the threshold voltage moving operation of said memory cell to said erase state is completed,
wherein said nonvolatile memory repeats said erase operation when the threshold voltage moving operation of said memory cell to that of an erase state is not yet completed, the erase operation of said nonvolatile memory ending when the threshold voltage of said memory cell is indicative of said erase state,
wherein said nonvolatile memory is capable of freeing said terminal when performing said erase operation and is capable of outputting a signal for indicating that said erase operation is being performed,
wherein said processing unit is capable of accessing other ones of said memories via said bus during a time said erase operation is being performed in said nonvolatile memory, and
wherein said processing unit is capable of inputting data from outside of said nonvolatile memory apparatus via said inputoutput terminal during a time said erase operation is being performed in said nonvolatile memory.
18. The nonvolatile memory apparatus according to claim 17,
wherein said processing unit performs a polling to said nonvolatile memory for detecting whether said erase operation is completed or not.
19. The nonvolatile memory apparatus according to claim 18,
wherein said processing unit is capable of designating a program operation for storing data to said nonvolatile memories except when said erase operation is being performed in those memories.
20. The nonvolatile memory apparatus according to claim 19,
wherein each nonvolatile memory contains a plurality of memory cells and a voltage generating circuit, which is capable of generating an erase voltage and a program voltage,
wherein said voltage generating circuit supplies said erase voltage to ones of said memory cells selected for said erase operation, and
wherein said voltage generating circuit supplies said program voltage to ones of said memory cells selected for said program operation.
21. A nonvolatile memory apparatus comprising:
a processing unit;
a plurality of memories; and
an inputoutput terminal,
wherein each of said memories has a terminal used for data input and for data output,
wherein said terminal of each of said memories and said inputoutput terminal are coupled to each other by a bus,
wherein at least one of said memories is a nonvolatile memory,
wherein said processing unit is capable of designating an erase operation to said nonvolatile memory for erasing data stored therein,
wherein said erase operation includes a threshold voltage moving operation and a verify operation,
wherein said threshold voltage moving operation is that in which a threshold voltage of a memory cell in a respective nonvolatile memory is moved to a threshold voltage range indicating an erase state,
wherein said verify operation determines whether the threshold voltage moving operation of said memory cell to said erase state is completed,
wherein said nonvolatile memory repeats said erase operation when the threshold voltage moving operation of said memory cell to that of an erase state is not yet completed, the erase operation of said nonvolatile memory ending when the threshold voltage of said memory cell is indicative of said erase state,
wherein said nonvolatile memory is capable of freeing said terminal when performing said erase operation and is capable of outputting a signal for indicating that said erase operation is being performed,
wherein said processing unit is capable of accessing other ones of said memories via said bus during a time said erase operation is being performed in said nonvolatile memory, and
wherein said processing unit is capable of outputting data to outside of said nonvolatile memory apparatus via said inputoutput terminal during a time said erase operation is being performed in said first nonvolatile memory.
22. The nonvolatile memory apparatus according to claim 21,
wherein said processing unit performs a polling to said nonvolatile memory for detecting whether said erase operation is completed or not.
23. The nonvolatile memory apparatus according to claim 22,
wherein said processing unit is capable of designating a program operation for storing data to said nonvolatile memories except when said erase operation is being performed in those memories.
24. The nonvolatile memory apparatus according to claim 23,
wherein each nonvolatile memory contains a plurality of memory cells and a voltage generating circuit, which is capable of generating an erase voltage and a program voltage,
wherein said voltage generating circuit supplies said erase voltage to ones of said memory cells selected for said erase operation, and
wherein said voltage generating circuit supplies said program voltage to ones of said memory cells selected for said program operation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method of manufacturing an ink jet head, comprising the steps of:
providing an actuator unit formed with a plurality of actuators extending in the same direction from a base portion to be in parallel with one another, each of said plurality of actuators being made of a plurality of piezoelectric elements extendable in a longitudinal direction causing tip ends of said plurality of actuators to move away from the base portion when an electrical signal is applied to the each of said plurality of actuators;
providing a diaphragm;
providing an ink channel unit formed with a plurality of ink channels corresponding to respective ones of said plurality of actuators individually;
dipping the tip ends of said plurality of actuators into an adhesive pond so that an adhesive agent clings to the tip ends or said plurality of actuators while maintaining a state in which an imaginary first line that connects the tip ends of said plurality of actuators is in parallel with an imaginary second line that Connects borders between immersed and non-immersed portions of said plurality of actuators;
adhering said actuator unit onto one surface of said diaphragm while abutting the tip ends of said plurality of actuators against the one surface of said diaphragm; and
attaching said ink channel unit to another surface of said diaphragm so that said plurality of ink channels are positioned in confronting relation with said respective ones of said plurality of actuators individually.
2. The method according to claim 1, wherein said actuator unit is further formed with at least two positioning members defining reference positions, and wherein the dipping step comprises bringing the imaginary second line to he substantially in coincidence with an imaginary third line that connects the reference positions when dipping the tip ends of said plurality of actuators into the adhesive pond.
3. The method according to claim 2, wherein said at least two positioning members extend from the base portion to be in parallel with said plurality of actuators.
4. The method according to claim 3, wherein said plurality of actuators are interposed between two of said at least two positioning members.
5. The method according to claim 1, wherein each of said plurality of actuators has an inactive portion at its tip end, said inactive portion being non-responsive to the electrical signal, and wherein the dipping step comprises bringing the imaginary second line to be within said inactive portion when dipping the tip ends of said plurality of actuators into the adhesive pond.
6. The method according to claim 1, wherein said actuator unit is further formed with at least two positioning members defining reference positions, and each of said plurality of actuators has an inactive portion at its tip end, said inactive portion being non-responsive to the electrical signal, and wherein the dipping step comprises bringing the imaginary second line to be substantially in coincidence with an imaginary third line that connects the reference positions and also to be within said inactive portion when dipping the tip ends or said plurality of actuators into the adhesive pond.
7. The method according to claim 1, wherein the dipping step comprises providing a dipping plate formed with a plurality of grooves corresponding to respective ones of said plurality of actuators, forming a plurality of adhesive ponds in said plurality of grooves by pouring an adhesive agent thereinto to be the same level, dipping the tip ends of said plurality of actuators into corresponding adhesive ponds, and drawing the tip ends of said plurality of actuators from the corresponding adhesive ponds.