What is claimed is:
1. An integrated circuit device comprising plural logic circuits and plural flip-flop circuits disposed between said plural logic circuits,
wherein each of said flip-flop circuits includes:
a first input port for receiving a scan test signal;
a second input port connected to corresponding one of said logic circuits for receiving, as a data signal, an output of said logic circuit according to a scan test signal input to said logic circuit;
a third input port for receiving a control signal for switching input to said flip-flop circuit between said scan test signal and said data signal;
a fourth input port for receiving a hold signal;
a first output port connected to said logic circuit for transferring said scan test signal to said logic circuit; and
a second output port for outputting said data signal and said scan test signal,
a scan test circuit is formed by serially connecting said plural flip-flop circuits by successively connecting said second output port of an arbitrary flip-flop circuit among said plural flip-flop circuits to said first input port of another of said flip-flop circuits disposed at a next stage, and
an output value output from said first output port is fixed in receiving said hold signal at said fourth input port.
2. The integrated circuit device of claim 1,
wherein said output value output from said first output port of each of said flip-flop circuits is fixed to a value held in receiving said hold signal.
3. The integrated circuit device of claim 2,
wherein said fourth input port of each of said flip-flop circuits also works as said third input port.
4. The integrated circuit device of claim 1,
wherein said output value output from said first output port of each of said flip-flop circuits is fixed to 1 or 0 regardless of a value held in receiving said hold signal.
5. An integrated circuit device comprising:
first and second circuits;
a first test circuit for testing said first circuit;
a second test circuit for testing said second circuit;
a clock supply part for supplying a clock signal to said first circuit and said second circuit;
a clock inverting part for inverting the clock signal supplied from said clock supply part and outputting an inverted clock signal; and
an output switching circuit disposed between said clock inverting part and said second circuit for receiving the clock signal and the inverted clock signal and outputting the inverted clock signal to said second circuit in testing said second circuit.
6. The integrated circuit device of claim 5,
wherein said first circuit is a logic circuit, and
said second circuit is a memory.
7. A method of testing an integrated circuit device, including plural logic circuits and plural flip-flop circuits disposed between said logic circuits, said flip-flop circuits being successively connected to form a scan test circuit, for conducting a scan test by repeating the steps of:
(a) conducting a holding operation for fixing an output signal from-each of said flip-flop circuits to a path connected to corresponding one of said logic circuits;
(b) with said output signal from said flip-flop circuits fixed in the step (a), conducting a shift operation for successively sending a scan test signal to said flip-flop circuits and for successively sending a data signal from each of said flip-flop circuits to outside of said integrated circuit device;
(c) conducting a hold releasing operation for releasing said output signal fixed in the step (a) after completing said shift operation; and
(d) conducting a capture operation for capturing an output signal of said logic circuit by each of said flip-flop circuits after the step (c).
8. The method of testing an integrated circuit device of claim 7,
wherein elements of each of said logic circuits are divided into plural groups,
said output signal is fixed to a value held by said flip-flop circuit in fixing said output signal in the step (a),
the step (c) is conducted with respect to each of said groups, and
after completing a first shift operation, the step (a) is carried out after the step (c) and before the step (d).
9. The method of testing an integrated circuit device of claim 7,
wherein elements of each of said logic circuits are divided into plural groups,
said output signal is fixed to a value held by said flip-flop circuit in fixing said output signal in the step (a),
the step (c) and the step (d) are carried out with respect to each of said groups in a manner that a capture operation of one group is carried out after a hold releasing operation of said group, and
after completing a first shift operation, the step (a) is carried out after the step (d).
10. The method of testing an integrated circuit device of claim 7,
wherein elements of each of said logic circuits are divided into plural groups,
said output signal is fixed to 1 or 0 regardless of a value held by said flip-flop circuit in fixing said output signal with respect to each of said groups in the step (a),
the step (c) and the step (d) are carried out with respect to each of said groups in a manner that a capture operation of one group is carried out after a hold releasing operation of said group, and
after a second shift operation, the step (a) is carried out after the step (d).
11. The method of testing an integrated circuit device of claim 7,
wherein elements of each of said logic circuits are divided into groups in a manner that peak power consumption during the scan test does not exceed an allowable value of power consumption of said integrated circuit device in general use.
12. A method of testing an integrated circuit device including first and second circuits, a first test circuit for testing said first circuit, a second test circuit for testing said second circuit and a clock supply part for supplying a clock signal to said first and second circuits,
wherein said first circuit is tested in accordance with the clock signal, and
said second circuit is tested, while said first circuit is being tested, in accordance with an inverted clock signal obtained by inverting the clock signal.
13. The method of testing an integrated circuit device of claim 12,
wherein said first circuit is a logic circuit, and
said second circuit is a memory.
14. A method of designing an integrated circuit device using a database including at least one core storing data necessary for designing said integrated circuit device,
wherein estimated information regarding power consumption during a test of said core is described in said database,
said estimated information regarding power consumption during a test of said core is used in selecting said core in higher level design, and
design information obtained as a result of the higher level design is used in lower level design.
15. The method of designing an integrated circuit device of claim 14,
wherein design using said estimated information is architecture design.
16. The method of designing an integrated circuit device of claim 15,
wherein said design information includes information for instructing, by using information of data flow among plural cores designed in said architecture design, to divide said cores into plural groups and to design a circuit structure capable of conducting a capture operation successively in the order from a group on a lower level side of said data flow.
17. The method of designing an integrated circuit device of claim 14,
said design information includes information on grouping for dividing said core into plural groups.
18. The method of designing an integrated circuit device of claim 14,
wherein said design information includes information on a test method.
19. The method of designing an integrated circuit device of claim 17,
wherein, when said database includes plural cores requiring different test methods, said design information includes test scheduling determined, with each of said test methods represented by a plane test pattern obtained by using time and a pin number as a coordinate, so as to minimize test time in consideration of restriction in a number of usable pins and not to allow peak power consumption to exceed an allowable value of power consumption of said integrated circuit device in general use.
20. A database for use in design of an integrated circuit device comprising plural cores each storing data necessary for designing said integrated circuit device, said database including information regarding power consumption of said cores during a test.
21. The database for use in design of an integrated circuit device of claim 20,
wherein said information regarding power consumption during a test includes at least one of:
an estimated value of peak power consumption of each of said cores;
an estimated maximum transition number of states of each of said cores, a circuit scale of each of said cores and power consumption of gates included in each of said cores; and
a circuit and a simulation pattern.
22. The database for use in design of an integrated circuit device of claim 21,
wherein said database includes information regarding a possible division number of each of said cores.
23. The database for use in design of an integrated circuit device of claim 22,
wherein said information regarding a possible division number of each of said cores includes at least one of:
a level at which power consumption during a shift operation is equal to peak power consumption in dividing said core;
a division number and power consumption of a core not accompanied by change in design of a test circuit; and
a division number and peak power consumption in every clock of a core not accompanied by change in design of a test circuit.
24. The database for use in design of an integrated circuit device of claim 20,
wherein said database includes information regarding division probability of each of said cores.
25. The database for use in design of an integrated circuit device of claim 24,
wherein said information regarding division probability of each of said cores includes at least one of a maximum possible division number of said core and a number of clock systems.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A unit (100) for filling the containers (2) with products (1), in particular pharmaceutical products (1), including:
a hopper (3,3a) for containing a mass of products (1) in bulk;
conveying means (5,6) for feeding said products (1) coming out of said hopper (3) along a predetermined path (P);
a filling station (SR), situated downstream of said conveying means (5,6) for filling said containers (2) with the products (1);
transporting means (4,C) for feeding said container to said filling station (SR); and
a station (SC) for checking said products (1), situated along said path (P) upstream of said filling station (SR);
said conveying means (5,6) including first conveying means (51,52,53), consisting of vibrating planes, and second conveying means (6) situated at said checking station (SC) between said conveying vibrating planes means (51,52,53) and said filling station (SR);
the unit being characterized in that said conveying means (5,6) further include product holding means (65) associated to said second conveying means (6) for keeping single products, so as to form, on said second conveying means (6) a succession of single spaced apart products (1), moving forward to said filling station (SR) along a part of said path (P):
2. A unit, according to claim 1, characterized in that said second conveying means (6) include a drum (6) rotating continuously, which moves said series of single products (1) to said filling station (SR) along a curved portion of said path (P).
3. A unit, according to claim 1 or 2, characterized in that said holding means (65) include a plurality of channels (66,67,68) communicating with a suction source in order to keep said products (1) on the second conveying means (6) along said portion of path (P) by effect of aspiration.
4. A unit, according to any of previous claims from 1 to 3, characterized in that said checking station (SC) includes optical means (7) for detecting said products (1), in order to identify determined physical features of said products (1) in bulk and in order to count the products passing to said filling station (SR), sending relative reference signals to a processing device (E) connected to the optical means (7).
5. A unit, according to claim 4, characterized in that said detecting means (7) include at least one videocamera (71), which detects information concerning features said products (1) kept on said second conveying means (6) along said portion of the path (P).
6. A unit, according to any of previous claims from 1 to 5, characterized in that said filling station (SR) includes a plurality of feeding channels (9), through which transiting products (1) pass; and deflecting means (8), aimed at detaching said products (1) held by said second conveying means (9) and at transferring the detached products (1) into said feeding channels (9).
7. A unit, according to claim 4 and 6, characterized in that said deflecting means (8) include a plurality of deflecting bars (81), each of which is associated to a relative feeding channel (9); each of said deflecting bars (81) being operated, by activating means controlled by said processing device (E), to move alternately between a detach position (A), in which a free end of the bar (81) is situated close to said second conveying means (6), in order to detach the products (1) conveyed by the second conveying means (6) and to allow the products (1) to enter a relative channel (9), and single products rejection position (B), in which a free end of the bar (81) is situated far from said second conveying means (6), in order to allow said products (1) to move on the second conveying means (6), until they reach a deflecting panel (85), that makes single products (1) fall into a rejection container (86).
8. A unit, according to any of previous claims 6 or 7, characterized in that each feeding channel (9) is defined by an upper housing (91), whose outlet mouth communicates with an inlet mouth of a lower housing (92), which is in turn equipped with a relative outlet mouth situated above a container (2); bulkhead means (93) being situated between said upper housing (91) and said lower housing (92), said bulkhead means (93) being operated, by said processing device (E), to move alternately between a position, in which said outlet mouth of said upper housing (91) is closed and a position, in which the same outlet mouth is open.
9. Unit, according to any of previous claims from 1 to 8, characterized in that said first vibrating planes conveying means (51,52,53) and said second conveying means (6) are equipped with a plurality of guides or grooves (54,64), on which the products (1) move; said holding means (65) acting on said grooves (64) of said second conveying means (6). to hold series of single products (1) along said portion of path (P).
10. A packaging machine (M), characterized in that it includes at least one unit (100) for filling containers (2) with products (1), in accordance with one or more of the previous claims from 1 to 9.