1. A digital-analog converter system, comprising:
a common mode adjustment module, determining a first value S according to a digital input D;
a pre-processing module, connecting to the common mode adjustment module for determining number of positive units which are turned on (Pa) and number of negative units which are turned on (Na) according to the first value S and the digital input D;
a digital-analog converter circuit, comprising M three-level switch elements, each three-level switch element has a positive unit capable of supplying a unit of positive electricity and a negative unit capable of supplying a unit of negative electricity, the digital-analog converter circuit generates a corresponding analog output according to Pa and Na; and
an assignment module, connecting to the pre-processing module and the digital-analog converter circuit for controlling the M three-level switch elements to supply positive or negative electricity in a predetermined order according to the first value S.
2. The digital-analog converter system of claim 1, wherein each three-level switch element supplies no electricity when the positive unit and the negative unit are both turned on or both turned off.
3. The digital-analog converter system of claim 1, further comprising a transistor that switches the positive unit and another transistor that switches the negative unit in each three-level switch element.
4. The digital-analog converter system of claim 1, wherein the number of the positive units which are turned on (Pa) and the number of the negative units which are turned on (Na) are determined according to Pa+Na=S and Pa\u2212Na=D.
5. The digital-analog converter system of claim 1, wherein M is an even number, further comprising:
the first value S equals M when the digital input D is even; and
the first value S equals M+1 or M\u22121 when the digital input D is odd.
6. The digital-analog converter system of claim 1, wherein M is an odd number, further comprising:
the first value S equals M when the digital input D is odd; and
the first value S equals M+1 or M\u22121 when the digital input D is even.
7. The digital-analog converter system of claim 1, wherein the assignment module comprising:
a first assignment circuit for turning on the positive units by increasing index progressively or by decreasing index progressively; and
a second assignment circuit for turning on the negative units by decreasing index progressively or by increasing index progressively.
8. The digital-analog converter system of claim 1, wherein the digital-analog converter system is an over-sampling DA converter system.
9. The digital-analog converter system of claim 1, wherein the digital-analog converter system is a sigma-delta converter.
10. A digital-analog converting method in a digital-analog converter system comprising M three-level switch elements, each three-level switch element has a positive unit capable of supplying a unit of positive electricity and a negative unit capable of supplying a unit of negative electricity, the method comprising:
determining a first value S according to a digital input D;
determining number of positive units which are turned on (Pa) and number of negative units which are turned on (Na) according to the first value S and the digital input D;
controlling the M three-level switch elements to supply positive or negative electricity in a predetermined order according to the first value S; and
generating a corresponding analog output according to Pa and Na.
11. The digital-analog converting method of claim 10, wherein each three-level switch element supplies no electricity when the positive unit and the negative unit are both turned on or both turned off.
12. The digital-analog converting method of claim 10, further comprising a transistor that switches the positive unit and another transistor that switches the negative unit in each three-level switch element.
13. The digital-analog converting method of claim 10, wherein the number of the positive units which are turned on (Pa) and the number of the negative units which are turned on (Na) are determined according to Pa+Na=S and Pa\u2212Na=D.
14. The digital-analog converting method of claim 10, wherein M is an even number, further comprising:
the first value S equals M when the digital input D is even; and
the first value S equals M+1 or M\u22121 when the digital input D is odd.
15. The digital-analog converting method of claim 14, further comprising:
when a preceding digital input D is an odd number and the first value S is M+1, on a next odd digital input D the first value S is M\u22121; or
when the preceding digital input D is an odd number and the first value S is M\u22121, on a next odd digital input D the first value S is M+1.
16. The digital-analog converting method of claim 10, wherein M is an odd number, further comprising:
the first value S equals M when the digital input D is odd; and
the first value S equals M+1 or M\u22121 when the digital input D is even.
17. The digital-analog converting method of claim 16, further comprising:
when a preceding digital input D is an even number and the first value S is M+1, on a next even digital input D the first value S is M\u22121; or
when the preceding digital input D is an even number and the first value S is M\u22121, on a next even digital input D the first value S is M+1.
18. The digital-analog converting method of claim 10, further comprising:
turning on the positive units by increasing index progressively and turning on the negative units by decreasing index progressively; or
turning on the positive units by decreasing index progressively and turning on the negative units by increasing index progressively.
19. The digital-analog converting method of claim 10, wherein the digital-analog converter system is an over-sampling DA converter system.
20. The digital-analog converting method of claim 10, wherein the digital-analog converter system is a sigma-delta converter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus comprising:
an analog to digital converter (ADC) that samples and quantizes an analog signal to a digital signal comprised of:
a doubling sampling digital to analog converter (DAC) and integrator that receives and amplitude multiplies the analog signal to reduce flicker noise; and
a 1-bit comparator that receives an output from the double sampling digital to analog converter (DAC), and generates the digital signal; and
a modulator that modulates the digital signal.
2. The apparatus of claim 1, wherein the ADC is a delta sigma converter that samples a difference between the analog signal a feedback signal of the double sampling DAC and integrator.
3. The apparatus of claim 1, wherein the ADC samples the analog signal based on the highest frequency of the analog signal.
4. The apparatus of claim 1, wherein the double sampling DAC and integrator includes a fully differential integrator that generates a fully differential voltage that is proportional to two times the analog signal.
5. The apparatus of claim 1, wherein the double sampling DAC and integrator includes a fully differential integrator that receives and integrates a feedback difference signal.
6. The apparatus of claim 1, wherein the double sampling DAC and integrator is a higher order loop filter.
7. The apparatus of claim 1, wherein the comparator receives a reference voltage as an input and the reference voltage determines the digital signal.
8. The apparatus of claim 7, wherein the reference voltage is loaded independently from the input.
9. A double sampling digital to analog converter (DAC) and integrator comprising:
an operational amplifier which operates as a fully differential integrator, and receives an analog input signal; wherein the operational amplifier amplitude multiplies the analog input signal to reduce flicker noise;
two or more sampling capacitors that sample the analog input signal; and
multiple switches that determine sampling state of the two or more sampling capacitors.
10. The double sampling DAC and integrator of claim 9, wherein the sampling capacitors perform sample and hold of the analog input signal.
11. The double sampling DAC and integrator of claim 9, wherein the sampling capacitors and charged in a first phase, and discharged in a second phase.
12. The double sampling DAC and integrator of claim 9, wherein the multiple switches are operated based on a clock input and feedback signal.
13. The double sampling DAC and integrator of claim 9, wherein the multiple switches are MOSFET switches.
14. The double sampling DAC and integrator of claim 9, wherein the double sampling DAC and integrator outputs one or more reference signals in a feedback loop.
15. The double sampling DAC and integrator of claim 9, wherein the double sampling DAC and integrator outputs a voltage that is proportional to two times the analog input voltage.
16. A method of converting an analog signal to a digital signal comprising:
receiving the analog signal;
charging one or more capacitors to a voltage value associated with the analog signal;
discharging the one or more capacitors;
charging one or more integrating capacitors upon the discharging; and
generating a fully differential sampled signal that is amplitude multiplied to Reduce flicker noise, based on the charging of the one or more integrating capacitors.
17. The method of claim 15, wherein the receiving includes a DC reference signal.
18. The method of claim 15, wherein the charging the one or more capacitors is reference loading independent.
19. The method of claim 15, wherein the charging the one or more capacitors is based on phases of a clocked signal.
20. The method of claim 15, wherein the charging the one or more capacitors is based on state conditions connecting the integrating capacitors.