1. A method for 18Ffluoride phase transfer, said method comprising the steps of:
trapping 18Ffluoride on a resin held within a microfluidic chamber;
eluting the 18Ffluoride with an eluent to form an eluate, and
optionally diluting the water concentration of said eluate to form a final 18Ffluoride solution.
2. The method of claim 1, wherein said eluent comprises potassium carbonate dissolved in water.
3. The method of claim 2, wherein said eluent further comprises acetonitrile and Kryptofix in a stoichiometric concentration matching the used carbonate concentration.
4. The method of claim 3, wherein said diluting step further comprises adding additional acetonitrile to said eluate.
5. The method of claim 1, wherein the water concentration of said final 18Ffluoride solution is between 0.1% and 0.7%.
6. The method of claim 1 wherein the water concentration of said final 18Ffluoride solution is \u22660.5%.
7. The method of claim 1, wherein said eluting step is performed using enough water to enable complete elution of the 18Ffluoride.
8. The method of claim 1, wherein said trapping step is performed using a (nanopak)(microchip).
9. The method of claim 1, wherein said resin is a functionalized polystyrene.
10. The method of claim 9, wherein said resin includes a bead size of about 60 microns in diameter.
11. A method for 18Fradiotracer synthesis comprising the steps of:
trapping 18Ffluoride on a resin held within a microfluidic chamber;
eluting the 18Ffluoride with an eluent to form an eluate;
optionally diluting the water concentration of said eluate to form a final 18Ffluoride solution; followed by
reacting said final 18Ffluoride solution with a labelling precursor to form an 18Fradiotracer.
12. A method of claim 11, wherein said trapping, eluting, and reacting steps are performed using a microchip for performing nucleophilic fluoridation phase transfer, said microchip comprising:
a microchip body comprising a first and second elongate body joined along a major surface of each said body;
an elongate microchannel defined between said first body and second bodies;
a first input port defined by said first body extending therethrough in fluid communication with said microchannel,
a first output port defined by said first body extending therethrough in fluid communication with said microchannel; and
a reservoir defined by an elongate portion of said microchannel at a location between said first input port and said first output port, wherein said resin is retained within said reservoir.
13. A method according to claim 12 wherein the reaction of said final 18Ffluoride solution with a labelling precursor to form an 18Fradiotracer comprises the following steps:
reaction of said final 18Ffluoride solution with a labelling precursor;
optional removal of any protecting groups; and
purification of the resultant 18Fradiotracer.
14. A method according to claim 12 wherein at least one of said labeling, deprotecting, and purifying steps is performed within a microfluidic device.
15. A method according to any one of claims 12 to 14 wherein all steps are performed within a single microfluidic device.
16. A method according to any one of claims 12 to 15 wherein the labelling precursor is mannose triflate and the 18Fradiotracer is 18FFDG.
17. A device for performing 18Ffluoride phase transfer, comprising:
An elongate tubular body having a first open end defining an entry port, a second open end defining an exit port, said tubular body defining an elongate reservoir extending in fluid communication between said entry and exit ports;
A filtration device spanning said reservoir adjacent said exit port; and
A resin positioned in said reservoir opposite said filtration device from said exit port, said resin sized to be retained within said reservoir by said filtration device.
18. A device of claim 17, wherein said filtration device comprises filter paper.
19. A device of claim 17, wherein said filtration device comprises a microporous copolymer.
20. A device of claim 17, wherein said resin comprises a functionalized polystyrene.
21. A device of claim 20, wherein said resin includes a bead size of about 60 microns in diameter.
22. A device of claim 17, wherein said tubular body is formed of Teflon.
23. A microchip for performing nucleophilic fluoridation phase transfer comprising:
a microchip body comprising a first and second elongate body joined along a major surface of each said body;
an elongate microchannel defined between said first body and second bodies;
a first input port defined by said first body extending therethrough in fluid communication with said microchannel,
a first output port defined by said first body extending therethrough in fluid communication with said microchannel;
a reservoir defined by an elongate portion of said microchannel at a location between said first input port and said first output port; and
a resin retained by said microchip body within said reservoir.
24. A microchip of claim 23, further comprising a first fill port defined by said first body and extending therethrough and a first channel segment defined between said first and second bodies extending in fluid communication between said second input port and said reservoir, said second input port and said first channel segment sized to allow passage of said resin therethrough into said reservoir.
25. A microchip of claim 24, wherein said microchip body retains said resin in said reservoir by defining a constriction at one end of said reservoir.
26. A microchip of claim 25, further comprising a first weir at said one end of said reservoir.
27. A microchip of claim 26, further comprising a second weir at the other end of said reservoir.
28. A microchip of claim 23, wherein at least a portion of said microchannel extends along a serpentine path.
29. A microchip of claim 23, further comprising a second fill port defined by said first body and extending therethrough and a second channel segment defined between said first and second bodies extending in fluid communication between said second fill port and said reservoir, said second port port and said second channel segment sized to allow passage of said resin therethrough into said reservoir.
30. A microchip of claim 23, wherein said reservoir further comprises an elongate straight segment of said microchannel.
31. A microchip of claim 23, wherein said reservoir further comprises a tear-shaped segment of said microchannel such that the width of said microchannel varies along the length of said reservoir.
32. A system for performing nucleophilic fluoridation phase transfer and labeling comprising:
(a) a trapping device for performing 18Ffluoride phase transfer, said traping device comprising:
an elongate tubular body having a first open end defining an entry port, a second open end defining an exit port, said tubular body defining an elongate reservoir extending in fluid communication between said entry and exit ports;
a filtration device spanning said reservoir adjacent said exit port;
a resin positioned in said reservoir opposite said filtration device from said exit port, said resin sized to be retained within said reservoir by said filtration device;
(b) a microchip for performing labeling, said microchip comprising
a microchip body comprising a first and second elongate body joined along a major surface of each said body;
an elongate microchannel defined between said first body and second bodies;
a first input port defined by said first body extending therethrough in fluid communication with said microchannel,
a first output port defined by said first body extending therethrough in fluid communication with said microchannel,
and
(c) an elongate hollow conduit extending between said exit port of said trapping device and said first input port of said microchip.
33. A system of claim 32, wherein said microchannel further comprises at least one segment extending along a spiraling path.
34. A microchip of claim 33, where said microchannel further comprises at least one segment extending along a counter-spiraling path.
35. A microchip for performing nucleophilic fluoridation phase transfer and labeling comprising:
a microchip body comprising a first and second elongate body joined along a major surface of each said body;
an elongate microchannel defined between said first body and second bodies;
a first input port defined by said first body extending therethrough in fluid communication with said microchannel,
a first output port defined by said first body extending therethrough in fluid communication with said microchannel;
a reservoir defined by an elongate portion of said microchannel at a location between said first input port and said first output port; and
a second input port defined by said first body extending therethrough in fluid communication with said microchannel at a junction between said reservoir and said output port;
wherein said microchannel includes a mixing segment extending between said junction and said output port.
36. A microchip of claim 35, further comprising a resin retained by said microchip body within said reservoir.
37. A microchip of claim 35, further comprising a third input port defined by said first body extending therethrough in fluid communication with said microchannel at a location between said first input port and said reservoir.
38. A microchip of claim 35, further defining a first fill port defined by said first body extending therethrough in direct fluid communication with said reservoir.
39. A microchip of claim 35, wherein said mixing segment further comprises a spiral-counterspiral flowpath.
40. A microchip for performing nucleophilic fluoridation labeling and deprotection comprising:
a microchip of claim 35, wherein said microchip further comprises
a second mixing segment of said microchannel at a location between said mixing segment and said output port; and
a fourth input port defined by said first body and extending therethrough in fluid communication with said microchannel at a location between said mixing segment and said second mixing segment.
41. A microchip for performing nucleophilic fluoridation phase transfer, labeling, deprotection and purification, comprising:
a microchip of claim 39, wherein said microchip further comprises
a second reservoir defined by an elongate portion of said microchannel at a location between said second mixing segment and said first output port; and
a fifth input port defined by said first body and extending therethrough in fluid communication with said microchannel at a location between said second mixing segment and said second reservoir.
42. A microchip of claim 41, further comprising a second output port defined by said first body and extending therethrough in fluid communication with said microchannel at a location between said second reservoir and said first output port.
43. A microchip of claim 42, further comprising a first weir extending across said reservoir at one end thereof.
44. A microchip of claim 43, further comprising a second weir extending across said reservoir at the other end thereof.
45. A microchip of claim 42, further comprising a first weir extending across said second reservoir at one end thereof.
46. A microchip of claim 45, further comprising a second weir extending across said reservoir at one the other end thereof.
47. A microchip of claim 35, wherein said second input port is in fluid communication with a source of precursor.
48. A system for performing nucleophilic fluoridation labeling and deprotection comprising:
a microchip of claim 35;
a resin retained by said microchip body within said reservoir;
a source of 18F in fluid communication with said first end of said reservoir;
a source of eluent in fluid communication with said first end of said reservoir and
a source of precursor in fluid communication with said second input port.
49. A microchip for performing nucleophilic fluoridation labeling and deprotection comprising:
a microchip of claim 40;
a resin retained by said microchip body within said reservoir;
a source of 18F in fluid communication with said first end of said reservoir;
a source of eluent in fluid communication with said first end of said reservoir;
a source of precursor in fluid communication with said second input port; and
a source of a deprotection agent in fluid communication with said fourth input port.
50. A system for performing nucleophilic fluoridation fluoridation phase transfer, labeling, deprotection and purification, comprising:
a microchip of claim 41;
a resin retained by said microchip body within said reservoir;
a source of 18F in fluid communication with said first end of said reservoir;
a source of eluent in fluid communication with said first end of said reservoir;
a source of precursor in fluid communication with said second input port;
a source of a deprotection agent in fluid communication with said fourth input port;
a source of a second eluent in fluid communication with said fifth input port.
51. A microchip of claim 23, wherein:
said first body is further comprised of a first and second layer, wherein said first layer defines a pathway for said microchannel, such that said microchannel is defined between second layer and said second body.
52. A microchip of claim 51, wherein said first layer, second layer and said first body further comprise a sheet of PMMA.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
encoding, by an encoder of a wireless communications terminal, a sequence of information bits of a source data signal based on a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code, wherein the encoding is performed based on frames of the sequence of information bits, each frame being of a length of kldpc information bits (i0, i1 . . . , ikldpc\u22121), and the output of the encoding comprises coded LDPC frames each being nldpc coded bits in length, and
wherein the structured parity check matrix is represented by tabular information of a format wherein each row represents occurrences of one values within a respective column of the parity check matrix, and the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the tabular information, and wherein the tabular information comprises a one of Tables 1a through 1d (below);
wherein the encoding comprises generating nldpc\u2212kldpc parity bits (p0, p1, . . . , pnldpc\u2212kldpc\u22121) for each frame of the sequence of information bits, wherein the generation of the parity bits comprises:
initializing parity bit accumulators for p0, p1, . . . , pnldpc\u2212kldpc\u22121 to zero;
accumulating information bit i0 at parity bit accumulator addresses specified in the first row of the table;
for the next group of m\u22121 information bits, iy (y=1, 2, . . . , m\u22121), accumulating each information bit at parity bit accumulator addresses {x+(y mod m)*q} mod (nldpc\u2212kldpc), wherein x denotes an address of a parity bit accumulator corresponding to the information bit i0, and q is a code-rate dependent constant (q=(nldpc\u2212k)m), and wherein m is a code-dependent constant and k=R*n (where R is the code rate);
accumulating im at parity bit accumulator addresses specified in the second row of the table, and, in a similar manner as for the group of m\u22121 information bits (above), accumulating each information bit of the next group of m\u22121 information bits iz, z=(m+1, m+2, . . . , 2m) at {x+(z mod m)*q} mod (nldpc\u2212kldpc), wherein x denotes the address of the parity bit accumulator corresponding to the information bit im (the entries of the second row of the table);
in a similar manner, for each subsequent group of m information bits, accumulating the information bits at parity bit addresses based on a next row of the table; and
after all of the information bits of the frame are accumulated, performing operations according to pi=pi\u2295pi-1, wherein for i=1, 2, . . . , (nldpc\u2212kldpc\u22121), each pi resulting from the operation for a given i is equal to the parity bit pi;
TABLE 1a
Address of Parity Bit Accumulators (Rate 1145) (nldpc = 16200)
9054 9186 12155 1000 7383 6459 2992 4723 8135 11250
2624 9237 7139 12238 11962 4361 5292 10967 11036 8105
2044 11996 5654 7568 7002 3549 4767 8767 2872 8345
6966 8473 5180 8084 3359 5051 9576 5139 1893 902
3041 3801 8252 11951 909 8535 1038 8400 3200 4585
5291 10484 10872
442 7516 3720
11469 769 10998
10575 1436 2935
6905 8610 11285
1873 5634 6383
TABLE 1b
Address of Parity Bit Accumulators (Rate 1445) (nldpc = 16200)
1606 3617 7973 6737 9495 4209 9209 4565 4250 7823 9384 400
4105 991 923 3562 3892 10993 5640 8196 6652 4653 9116 7677
6348 1341 5445 1494 7799 831 4952 5106 3011 9921 6537 8476
7854 5274 8572 3741 5674 11128 4097 1398 5671 7302 8155 2641
6548 2103 590 5749 5722 10 2682 1063 633 2949 207 6065
2828 6366 4766 399 935 7611 84 150 3146
5363 7455 7140
9297 482 4848
8458 1631 5344
5729 6767 4836
11019 4463 3882
4107 9610 5454
11137 4328 6307
3260 7897 3809
TABLE 1c
Address of Parity Bit Accumulators (Rate 2645) (nldpc = 16200)
6106 5389 698 6749 6294 1653 1984 2167 6139 6095 3832 2468 6115
4202 2362 1852 1264 3564 6345 498 6137 3908 3302 527 2767 6667
3422 1242 1377 2238 2899 1974 1957 261 3463 4994 215 2338
3016 5109 6533 2665 5300 4908 4967 5787 726 229 1970 2789
6146 5765 6649 2871 884 1670 2597 5058 3659 6594 5042 304
5521 2811 0 4214 2626 2211 1236 3771 852 6356 6797 3463
1523 1830 3938 5593 2128 5791 3421 3680 6692 1377 3808 3475
5551 6035 2247 3662 759 6783 116 6380 4586 3367 1 5003
3518 6557 6510
1830 839 4421
5431 5959 6152
3174 5113 4520
5399 1303 2496
2841 741 220
2731 1830 4193
1875 3935 223
9 4720 423
3107 2676 840
1950 6177 6457
4091 94 5102
1907 6050 3455
714 3 559
502 4268 4164
1019 5558 271
6127 854 3221
959 5337 2735
TABLE 1d
Address of Parity Bit Accumulators (Rate 3245) (nldpc = 16200)
2686 655 2308 1603 336 1743 2778 1263 3555 185 4212 621
286 2994 2599 2265 126 314 3992 4560 2845 2764 2540 1476
2670 3599 2900 2281 3597 2768 4423 2805 836 130 1204 4162
1884 4228 1253 2578 3053 3650 2587 4468 2784 1644 1490 4655
4258 1699 4363 4555 3810 4046 3806 344 2459 4067 3327 3510
1021 2741 2528 2168 2820
254 1080 616
1465 4192 2972
2356 2976 1534
4412 1937 2724
1430 3024 600
1952 2136 3573
3009 3123 1288
4553 2299 806
2997 402 4330
3302 4567 698
2364 498 3146
1809 647 992
3512 32 4301
1238 251 450
1657 737 641
560 1720 2893
1689 2206 902
3998 1784 2094
2090 3126 1201
1565 764 3473
891 903 2413
2286 2900 2348
3026 2033 1502
2404 1243 556
308 2222 3825
1523 3311 389;
and
wherein the encoding processes the source data signal for transmission over a wireless communications channel.
2. The method of claim 1, wherein the LDPC code is of a structure that facilitates use of a plurality of parallel engines for decoding the coded signal.
3. The method of claim 1, wherein nldpc=16200, and m=360.
4. The method of claim 1, further comprising:
modulating, by a modulator of the wireless communications terminal, the coded LDPC frames according to according to one of the following modulation types: \u03c02 BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8-PSK (Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying), and 32-APSK.
5. The method of claim 1, wherein the sequence of information bits of the source data signal is segmented into a series of baseband frames, and the method further comprises:
encoding each baseband frame based on a t-error Bose Chaudhuri Hocquenghem (BCH) code, wherein the BCH encoding comprises an outer coding and the LDPC encoding comprises an inner coding.
6. The method of claim 5, further comprising:
interleaving, by an interleaver of the wireless communications terminal, each coded LDPC frame using a block interleaver, wherein the coded bits are written into an interleaver array on a column-by-column basis and read out on a row-by-row basis, and the output of the interleaving comprises coded FEC frames.
7. The method of claim 6, wherein the interleaver array comprises a number of rows and a number of columns, and the coded bits are read out of each row in a predetermined order, and wherein:
the number of columns in the interleaver array is based on a selected modulation scheme as specified in the following table:
Modulation
# of Interleaver
Scheme
Array Columns
\u20028 PSK
3
16 APSK
4
32 APSK
\u20095;
and
the order in which the coded bits are read out of each row of the interleaver array is based on the selected modulation scheme and a selected code rate as specified in the following table (where the numbers reflecting the bit interleaver patterns chronologically signify a respective column of the row being read out, with \u201c0\u201d signifying the leftmost column):
Bit Interleaver
Modulation
Code Rate
Pattern
\u20028 PSK
2645
1-0-2
16 APSK
2645
2-1-3-0
\u20028 PSK
3245
0-1-2
16 APSK
3245
0-1-2-3
32 APSK
3245
1-0-4-2-3.
8. The method of claim 7, further comprising:
modulating the coded FEC frames according to the selected modulation scheme, wherein the selected modulation scheme comprises one of the following modulation types: \u03c02 BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8-PSK (Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying), and 32-APSK;
wherein, in the case of \u03c02 BPSK or QPSK, the coded FEC frames are not interleaved.
9. A method comprising:
encoding, by an encoder of a wireless communications terminal, a sequence of information bits of a source data signal based on a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code, wherein the encoding is performed based on frames of the sequence of information bits, each frame being of a length of kldpc information bits (i0, i1, . . . , ikldpc\u22121), and the output of the encoding comprises coded LDPC frames each being nldpc coded bits in length, and
wherein the structured parity check matrix is represented by tabular information of a format wherein each row represents occurrences of one values within a respective column of the parity check matrix, and the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the tabular information, and wherein the tabular information comprises a one of Tables 9a through 9b (below);
wherein the encoding comprises generating nldpc\u2212kldpc parity bits (p0, p1, . . . , pnldpc\u2212kldpc\u22121) for each frame of the sequence of information bits, wherein the generation of the parity bits comprises:
initializing parity bit accumulators for p0, p1, . . . , pnldpc\u2212kldpc\u22121 to zero;
accumulating information bit i0 at parity bit accumulator addresses specified in the first row of the table;
for the next group of m\u22121 information bits, iy (y=1, 2, . . . , m\u22121), accumulating each information bit at parity bit accumulator addresses {x+(y mod m)*q} mod (nldpc\u2212kldpc), wherein x denotes an address of a parity bit accumulator corresponding to the information bit i0, and q is a code-rate dependent constant (q=(nldpc\u2212k)m), and wherein m is a code dependent constant and k=R*n (where R is the code rate);
accumulating im at parity bit accumulator addresses specified in the second row of the table, and, in a similar manner as for the group of m\u22121 information bits (above), accumulating each information bit of the next group of m\u22121 information bits iz, z=(m+1, m+2, . . . , 2m) at {x+(z mod m)*q} mod (nldpc\u2212kldpc), wherein x denotes the address of the parity bit accumulator corresponding to the information bit im (the entries of the second row of the table);
in a similar manner, for each subsequent group of m information bits, accumulating the information bits at parity bit addresses based on a next row of the table; and
after all of the information bits of the frame are accumulated, performing operations according to pi=pi\u2295pi-1, wherein for i=1, 2, . . . , (nldpc\u2212kldpc\u22121), each pi resulting from the operation for a given i is equal to the parity bit pi;
wherein nldpc=16200, and m=360;
TABLE 9a
Address of Parity Bit Accumulators (Rate 35) (nldpc = 16200)
2765 5713 6426 3596 1374 4811 2182 544 3394 2840 4310 771
4951 211 2208 723 1246 2928 398 5739 265 5601 5993 2615
210 4730 5777 3096 4282 6238 4939 1119 6463 5298 6320 4016
4167 2063 4757 3157 5664 3956 6045 563 4284 2441 3412 6334
4201 2428 4474 59 1721 736 2997 428 3807 1513 4732 6195
2670 3081 5139 3736 1999 5889 4362 3806 4534 5409 6384 5809
5516 1622 2906 3285 1257 5797 3816 817 875 2311 3543 1205
4244 2184 5415 1705 5642 4886 2333 287 1848 1121 3595 6022
2142 2830 4069 5654 1295 2951 3919 1356 884 1786 396 4738
0 2161 2653
1 1380 1461
2 2502 3707
3 3971 1057
4 5985 6062
5 1733 6028
6 3786 1936
7 4292 956
8 5692 3417
9 266 4878
10 4913 3247
11 4763 3937
12 3590 2903
13 2566 4215
14 5208 4707
15 3940 3388
16 5109 4556
17 4908 4177
TABLE 9b
Address of Parity Bit Accumulators (Rate 23) (nldpc = 16200)
0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 2622
1 122 1516 3448 2880 1407 1847 3799 3529 373 971 4358 3108
2 259 3399 929 2650 864 3996 3833 107 5287 164 3125 2350
3 342 3529
4 4198 2147
5 1880 4836
6 3864 4910
7 243 1542
8 3011 1436
9 2167 2512
10 4606 1003
11 2835 705
12 3426 2365
13 3848 2474
14 1360 1743
0 163 2536
1 2583 1180
2 1542 509
3 4418 1005
4 5212 5117
5 2155 2922
6 347 2696
7 226 4296
8 1560 487
9 3926 1640
10 149 2928
11 2364 563
12 635 688
13 231 1684
14 1129 3894;
and
interleaving, by an interleaver of the wireless communications terminal, each coded LDPC frame using a block interleaver, wherein the coded bits are written into an interleaver array on a column-by-column basis and read out on a row-by-row basis, and the output of the interleaving comprises coded FEC frames, wherein the interleaver array comprises a number of rows and a number of columns, and the coded bits are read out of each row in a predetermined order, and wherein the number of columns in the interleaver array is based on a selected modulation scheme as specified in the following table:
Modulation
# of Interleaver
Scheme
Array Columns
16 APSK
4
32 APSK
\u20095;
and
the order in which the coded bits are read out of each row of the interleaver array is based on the selected modulation scheme and a selected code rate as specified in the following table (where the numbers reflecting the bit interleaver patterns chronologically signify a respective column of the row being read out, with \u201c0\u201d signifying the leftmost column):
Bit Interleaver
Modulation
Code Rate
Pattern
16 APSK
35
3-2-0-1
32 APSK
23
4-1-3-2-0;
and
wherein the encoding and interleaving process the source data signal for transmission over a wireless communications channel.
10. The method of claim 9, wherein the sequence of information bits of the source data signal is segmented into a series of baseband frames, and the method further comprises:
encoding each baseband frame based on a t-error Bose Chaudhuri Hocquenghem (BCH) code, wherein the BCH encoding comprises an outer coding and the LDPC encoding comprises an inner coding.
11. The method of claim 9, further comprising:
modulating, by a modulator of the wireless communications terminal, the coded FEC frames according to the respective modulation scheme.
12. A wireless communications terminal apparatus, comprising:
an encoder configured to encode a sequence of information bits of a source data signal on a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code, wherein the encoding is performed based on frames of the source data sequence of information bits, each frame being of a length of kldpc information bits (i0, i1, . . . , ikldpc\u22121), and the output of the encoding comprises coded LDPC frames each being nldpc coded bits in length, and
wherein the structured parity check matrix is represented by tabular information of a format wherein each row represents occurrences of one values within a respective column of the parity check matrix, and the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the tabular information, and wherein the tabular information comprises a one of Tables 12a through 12d (below);
wherein the encoding comprises generating nldpc\u2212kldpc parity bits (p0, p1, . . . , pnldpc\u2212kldpc\u22121) for each frame of the sequence of information bits, wherein the generation of the parity bits comprises:
initializing parity bit accumulators for p0, p1, . . . , pnldpc\u2212kldpc\u22121 to zero;
accumulating information bit i0 at parity bit accumulator addresses specified in the first row of the table;
for the next group of m\u22121 information bits, iy (y=1, 2, . . . , m\u22121), accumulating each information bit at parity bit accumulator addresses {x+(y mod m)*q} mod (nldpc\u2212kldpc), wherein x denotes an address of a parity bit accumulator corresponding to the information bit i0, and q is a code-rate dependent constant (q=(nldpc\u2212k)m), and wherein m is a code-dependent constant and k=R*n (where R is the code rate);
accumulating im at parity bit accumulator addresses specified in the second row of the table, and, in a similar manner as for the group of m\u22121 information bits (above), accumulating each information bit of the next group of m\u22121 information bits iz, z=(m+1, m+2, . . . , 2m) at {x+(z mod m)*q} mod (nldpc\u2212kldpc), wherein x denotes the address of the parity bit accumulator corresponding to the information bit im (the entries of the second row of the table);
in a similar manner, for each subsequent group of m information bits, accumulating the information bits at parity bit addresses based on a next row of the table; and
after all of the information bits of the frame are accumulated, performing operations according to pi=pi\u2295pi-1, wherein for i=1, 2, . . . , (nldpc\u2212kldpc\u22121), each pi resulting from the operation for a given i is equal to the parity bit pi;
TABLE 12a
Address of Parity Bit Accumulators (Rate 1145) (nldpc = 16200)
9054 9186 12155 1000 7383 6459 2992 4723 8135 11250
2624 9237 7139 12238 11962 4361 5292 10967 11036 8105
2044 11996 5654 7568 7002 3549 4767 8767 2872 8345
6966 8473 5180 8084 3359 5051 9576 5139 1893 902
3041 3801 8252 11951 909 8535 1038 8400 3200 4585
5291 10484 10872
442 7516 3720
11469 769 10998
10575 1436 2935
6905 8610 11285
1873 5634 6383
TABLE 12b
Address of Parity Bit Accumulators (Rate 1445) (nldpc = 16200)
1606 3617 7973 6737 9495 4209 9209 4565 4250 7823 9384 400
4105 991 923 3562 3892 10993 5640 8196 6652 4653 9116 7677
6348 1341 5445 1494 7799 831 4952 5106 3011 9921 6537 8476
7854 5274 8572 3741 5674 11128 4097 1398 5671 7302 8155 2641
6548 2103 590 5749 5722 10 2682 1063 633 2949 207 6065
2828 6366 4766 399 935 7611 84 150 3146
5363 7455 7140
9297 482 4848
8458 1631 5344
5729 6767 4836
11019 4463 3882
4107 9610 5454
11137 4328 6307
3260 7897 3809
TABLE 12c
Address of Parity Bit Accumulators (Rate 2645) (nldpc = 16200)
6106 5389 698 6749 6294 1653 1984 2167 6139 6095 3832 2468 6115
4202 2362 1852 1264 3564 6345 498 6137 3908 3302 527 2767 6667
3422 1242 1377 2238 2899 1974 1957 261 3463 4994 215 2338
3016 5109 6533 2665 5300 4908 4967 5787 726 229 1970 2789
6146 5765 6649 2871 884 1670 2597 5058 3659 6594 5042 304
5521 2811 0 4214 2626 2211 1236 3771 852 6356 6797 3463
1523 1830 3938 5593 2128 5791 3421 3680 6692 1377 3808 3475
5551 6035 2247 3662 759 6783 116 6380 4586 3367 1 5003
3518 6557 6510
1830 839 4421
5431 5959 6152
3174 5113 4520
5399 1303 2496
2841 741 220
2731 1830 4193
1875 3935 223
9 4720 423
3107 2676 840
1950 6177 6457
4091 94 5102
1907 6050 3455
714 3 559
502 4268 4164
1019 5558 271
6127 854 3221
959 5337 2735
TABLE 12d
Address of Parity Bit Accumulators (Rate 3245) (nldpc = 16200)
2686 655 2308 1603 336 1743 2778 1263 3555 185 4212 621
286 2994 2599 2265 126 314 3992 4560 2845 2764 2540 1476
2670 3599 2900 2281 3597 2768 4423 2805 836 130 1204 4162
1884 4228 1253 2578 3053 3650 2587 4468 2784 1644 1490 4655
4258 1699 4363 4555 3810 4046 3806 344 2459 4067 3327 3510
1021 2741 2528 2168 2820
254 1080 616
1465 4192 2972
2356 2976 1534
4412 1937 2724
1430 3024 600
1952 2136 3573
3009 3123 1288
4553 2299 806
2997 402 4330
3302 4567 698
2364 498 3146
1809 647 992
3512 32 4301
1238 251 450
1657 737 641
560 1720 2893
1689 2206 902
3998 1784 2094
2090 3126 1201
1565 764 3473
891 903 2413
2286 2900 2348
3026 2033 1502
2404 1243 556
308 2222 3825
1523 3311 389;
and
wherein the encoding processes the source data signal for transmission over a wireless communications channel.
13. The apparatus of claim 12, wherein the LDPC code is of a structure that facilitates use of a plurality of parallel engines for decoding the coded signal.
14. The apparatus of claim 12, wherein nldpc=16200, and m=360.
15. The apparatus of claim 12, further comprising:
a modulator configured to modulate the coded LDPC frames according to according to one of the following modulation types: \u03c02 BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8-PSK (Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying), and 32-APSK.
16. The apparatus of claim 12, wherein the sequence of information bits of the source data signal is segmented into a series of baseband frames, and wherein the encoder is further configured to encode each baseband frame based on a t-error Bose Chaudhuri Hocquenghem (BCH) code, wherein the BCH encoding comprises an outer coding and the LDPC encoding comprises an inner coding.
17. The apparatus of claim 16, further comprising:
an interleaver configured to interleave each coded LDPC frame, wherein the coded bits are written into an interleaver array on a column-by-column basis and read out on a row-by-row basis, and the output of the interleaving comprises coded FEC frames.
18. The apparatus of claim 17, wherein the interleaver array comprises a number of rows and a number of columns, and the coded bits are read out of each row in a predetermined order, and wherein:
the number of columns in the interleaver array is based on a selected modulation scheme as specified in the following table:
Modulation
# of Interleaver
Scheme
Array Columns
\u20028 PSK
3
16 APSK
4
32 APSK
\u20095;
and
the order in which the coded bits are read out of each row of the interleaver array is based on the selected modulation scheme and a selected code rate as specified in the following table (where the numbers reflecting the bit interleaver patterns chronologically signify a respective column of the row being read out, with \u201c0\u201d signifying the leftmost column):
Bit Interleaver
Modulation
Code Rate
Pattern
\u20028 PSK
2645
1-0-2
16 APSK
2645
2-1-3-0
\u20028 PSK
3245
0-1-2
16 APSK
3245
0-1-2-3
32 APSK
3245
1-0-4-2-3.
19. The apparatus of claim 18, wherein the modulator is further configured to modulate the coded FEC frames according to the selected modulation scheme, wherein the selected modulation scheme comprises one of the following modulation types: \u03c02 BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8-PSK (Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying), and 32-APSK; and wherein, in the case of \u03c02 BPSK or QPSK, the coded FEC frames are not interleaved.
20. A wireless communications terminal apparatus, comprising:
an encoder configured to encode a sequence of information bits of a source data signal based on a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code, wherein the encoding is performed based on frames of the sequence of information bits, each frame being of a length of kldpc information bits (i0, i1, . . . , ikldpc\u22121), and the output of the encoding comprises coded LDPC frames each being nldpc coded bits in length, and
wherein the structured parity check matrix is represented by tabular information of a format wherein each row represents occurrences of one values within a respective column of the parity check matrix, and the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the tabular information, and wherein the tabular information comprises a one of Tables 20a through 20b (below);
wherein the encoding comprises generating nldpc\u2212kldpc parity bits (p0, p1, . . . , pnldpc\u2212kldpc\u22121) for each frame of the sequence of information bits, wherein the generation of the parity bits comprises:
initializing parity bit accumulators for p0, p1, . . . , pnldpc\u2212kldpc\u22121 to zero;
accumulating information bit i0 at parity bit accumulator addresses specified in the first row of the table;
for the next group of m\u22121 information bits, iy (y=1, 2, . . . , m\u22121), accumulating each information bit at parity bit accumulator addresses {x+(y mod m)*q} mod (nldpc\u2212kldpc), wherein x denotes an address of a parity bit accumulator corresponding to the information bit i0, and q is a code-rate dependent constant (q=(nldpc\u2212k)m), and wherein m is a code-dependent constant and k=R*n (where R is the code rate);
accumulating im at parity bit accumulator addresses specified in the second row of the table, and, in a similar manner as for the group of m\u22121 information bits (above), accumulating each information bit of the next group of m\u22121 information bits iz, z=(m+1, m+2, . . . , 2m) at {x+(z mod m)*q} mod (nldpc\u2212kldpc), wherein x denotes the address of the parity bit accumulator corresponding to the information bit im (the entries of the second row of the table);
in a similar manner, for each subsequent group of m information bits, accumulating the information bits at parity bit addresses based on a next row of the table; and
after all of the information bits of the frame are accumulated, performing operations according to pi=pi\u2295pi-1, wherein for i=1, 2, . . . , (nldpc\u2212kldpc\u22121), each pi resulting from the operation for a given i is equal to the parity bit pi;
wherein nldpc=16200, and m=360;
TABLE 20a
Address of Parity Bit Accumulators (Rate 35) (nldpc = 16200)
2765 5713 6426 3596 1374 4811 2182 544 3394 2840 4310 771
4951 211 2208 723 1246 2928 398 5739 265 5601 5993 2615
210 4730 5777 3096 4282 6238 4939 1119 6463 5298 6320 4016
4167 2063 4757 3157 5664 3956 6045 563 4284 2441 3412 6334
4201 2428 4474 59 1721 736 2997 428 3807 1513 4732 6195
2670 3081 5139 3736 1999 5889 4362 3806 4534 5409 6384 5809
5516 1622 2906 3285 1257 5797 3816 817 875 2311 3543 1205
4244 2184 5415 1705 5642 4886 2333 287 1848 1121 3595 6022
2142 2830 4069 5654 1295 2951 3919 1356 884 1786 396 4738
0 2161 2653
1 1380 1461
2 2502 3707
3 3971 1057
4 5985 6062
5 1733 6028
6 3786 1936
7 4292 956
8 5692 3417
9 266 4878
10 4913 3247
11 4763 3937
12 3590 2903
13 2566 4215
14 5208 4707
15 3940 3388
16 5109 4556
17 4908 4177
TABLE 20b
Address of Parity Bit Accumulators (Rate 23) (nldpc = 16200)
0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 2622
1 122 1516 3448 2880 1407 1847 3799 3529 373 971 4358 3108
2 259 3399 929 2650 864 3996 3833 107 5287 164 3125 2350
3 342 3529
4 4198 2147
5 1880 4836
6 3864 4910
7 243 1542
8 3011 1436
9 2167 2512
10 4606 1003
11 2835 705
12 3426 2365
13 3848 2474
14 1360 1743
0 163 2536
1 2583 1180
2 1542 509
3 4418 1005
4 5212 5117
5 2155 2922
6 347 2696
7 226 4296
8 1560 487
9 3926 1640
10 149 2928
11 2364 563
12 635 688
13 231 1684
14 1129 3894;
and
wherein the apparatus further comprises an interleave configured to interleave each coded LDPC frame using a block interleaver, wherein the coded bits are written into an interleaver array on a column-by-column basis and read out on a row-by-row basis, and the output of the interleaving comprises coded FEC frames,
wherein the interleaver array comprises a number of rows and a number of columns, and the coded bits are read out of each row in a predetermined order, wherein the number of columns in the interleaver array is based on a selected modulation scheme as specified in the following table:
Modulation
# of Interleaver
Scheme
Array Columns
16 APSK
4
32 APSK
5;
and
wherein the order in which the coded bits are read out of each row of the interleaver array is based on the selected modulation scheme and a selected code rate as specified in the following table (where the numbers reflecting the bit interleaver patterns chronologically signify a respective column of the row being read out, with \u201c0\u201d signifying the leftmost column):
Bit Interleaver
Modulation
Code Rate
Pattern
16 APSK
35
3-2-0-1
32 APSK
23
4-1-3-2-0;
and
wherein the encoding and interleaving process the source data signal for transmission over a wireless communications channel.
21. The apparatus of claim 20, wherein the sequence of information bits of the source data signal is segmented into a series of baseband frames, and wherein the encoder is further configured to encode each baseband frame based on a t-error Bose Chaudhuri Hocquenghem (BCH) code, wherein the BCH encoding comprises an outer coding and the LDPC encoding comprises an inner coding.
22. The apparatus of claim 20, further comprising:
a modulator configured to modulate the coded FEC frames according to the respective modulation scheme.