1. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor,
a second layer composed of a group III nitride semiconductor, and
a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer;
wherein a channel is formed in at least one of: (1) the first layer, (2) the second layer, (3) the region between the first layer and the second layer; and
wherein the conductivity type of the second layer is inversed with respect to the conductivity type of carriers flowing in the channel.
2. The semiconductor device as described in claim 1, wherein the second layer is in contact with an electrode for leading out carriers with the conductivity type inversed with respect to that of the carriers flowing in the channel from the device.
3. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor of a first conductivity type,
a second layer composed of a group III nitride semiconductor of a second conductivity type, and
a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer, and the first layer and the second layer are in contact with each other; and
wherein the band gap of the first layer is larger than the band gap of the second layer.
4. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor of a first conductivity type,
a second layer composed of a group III nitride semiconductor of a second conductivity type,
a third layer composed of a group III nitride semiconductor of the first conductivity type, and a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer;
wherein the third layer has a region formed between the first layer and the second layer; and
wherein the band gap of the third layer is less than the band gap of the first layer.
5. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor of a first conductivity type,
a second layer composed of a group III nitride semiconductor of a second conductivity type,
a third layer composed of a group III nitride semiconductor, and
a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer;
wherein the third layer has a region formed between the first layer and the second layer; and
wherein the band gap of the third layer is less than the band gap of the first layer and the second layer.
6. The semiconductor device as described in claim 5, wherein the third layer is composed of a substantially true group III nitride semiconductor.
7. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor of a first conductivity type,
a second layer composed of a group III nitride semiconductor of a second conductivity type, and
a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer; and
wherein the thickness of the first layer is not more than the thickness of a depleted layer extending from a boundary between the first layer and the second layer to the first layer side when no electric voltage is applied to the gate electrode.
8. A field-effect transistor comprising:
a gate electrode,
a first layer composed of a group III nitride semiconductor of a first conductivity type, and
a second layer composed of a group III nitride semiconductor of a second conductivity type located on a side of the first layer opposite to the gate electrode.
9. The field-effect transistor as described in claim 8, wherein the first layer and second layer are in direct contact with each other, and the band gap of the first layer is larger than the band gap of the second layer.
10. The field-effect transistor as described in claim 8, wherein a third layer having a band gap smaller than the band gaps of the first layer and the second layer is located between the first layer and second layer.
11. The field-effect transistor as described in claim 10, wherein the third layer is composed of a true group III nitride semiconductor.
12. The field-effect transistor as described in claim 8, wherein a third layer composed of a group III nitride semiconductor of the first conductivity type and having a band gap smaller than the band gap of the first layer is located between the first layer and second layer.
13. The field-effect transistor as described in claim 8 that operates in a normally off condition, wherein a depleted layer expanding from the second layer to the first layer depletes the entire first layer when no electric voltage is applied to the gate electrode.
14. The field-effect transistor as described in claim 13, further comprising a gate insulating film disposed between the gate electrode and the first layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A parasitic element extracting apparatus comprising:
wire congestion calculating means for calculating a degree of wire congestion in a wiring area, which is placed in a layout of a semiconductor circuit, according to both the number of wires arranged in the wiring area and the number of wires possible to be arranged in the wiring area;
dummy wiring area judging means for pre-setting a reference degree of the wire congestion relating to the arrangement of dummy wire, and comparing the degree of the wire congestion in the wiring area of the semiconductor circuit calculated by the wire congestion calculating means with the reference degree of the wire congestion to judge whether or not dummy wire is arranged in the wiring area for which the degree of the wire congestion is calculated by the wire congestion calculating means;
dummy wiring assuming means for setting an additional amount of the dummy wire according to the degree of the wire congestion in the wiring area of the semiconductor circuit calculated by the wire congestion calculating means in cases where it is judged by the dummy wiring area judging means that the dummy wire is arranged in the wiring area, and assuming a circuit layout of the wiring area on condition that the dummy wire, of which the additional amount is set, is arranged in the wiring area; and
parasitic element extracting means for extracting information of a parasitic element of the semiconductor circuit from a layout of the semiconductor circuit in which the circuit layout of the wiring area assumed in the dummy wiring assuming step is included.
2. A parasitic element extracting apparatus according to claim 1, wherein information of wire capacitance andor inductance is extracted as the information of the parasitic element of the semiconductor circuit by the parasitic element extracting means, a value of the wire capacitance, of which the information is extracted from the layout of the semiconductor circuit, is set by the parasitic element extracting means to be higher than a value of the wire capacitance existing in the wiring area in which no dummy wire is arranged, and a value of the inductance, of which the information is extracted from the layout of the semiconductor circuit, is set by the parasitic element extracting means to be lower than a value of the inductance existing in the wiring area in which no dummy wire is arranged.
3. A parasitic element extracting apparatus according to claim 1, wherein a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated by the dummy wiring assuming means according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set by the dummy wiring assuming means, and the circuit layout of the wiring area is assumed by the dummy wiring assuming means so as to increase the adjacent wire existence probabilities of the wires of the wiring area at equal rates.
4. A parasitic element extracting apparatus according to claim 1, wherein a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated by the dummy wiring assuming means according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set by the dummy wiring assuming means, and the circuit layout of the wiring area is assumed by the dummy wiring assuming means so as to equally increase the adjacent wire existence probabilities of the wires of the wiring area to a fixed adjacent wire existence probability.
5. A parasitic element extracting method comprising:
a wire congestion calculating step for calculating a degree of wire congestion in a wiring area of a semiconductor circuit, according to both the number of wires arranged in the wiring area and the number of wires possible to be arranged in the wiring area;
a dummy wiring area judging step for comparing the degree of the wire congestion calculated in the wire congestion calculating step with a reference degree of the wire congestion relating to the arrangement of dummy wire, and judging whether or not dummy wire is arranged in the wiring area for which the degree of the wire congestion is calculated in the wire congestion calculating step;
a dummy wiring assuming step for setting an additional amount of the dummy wire according to the degree of the wire congestion in the wiring area calculated in the wire congestion calculating step in cases where it is judged in the dummy wiring area judging step that the dummy wire is arranged in the wiring area, and assuming a circuit layout of the wiring area on condition that the dummy wire, of which the additional amount is set, is arranged in the wiring area; and
a parasitic element extracting step for extracting information of a parasitic element of the semiconductor circuit from a layout of the semiconductor circuit in which the circuit layout of the wiring area assumed in the dummy wiring assuming step is included.
6. A parasitic element extracting method according to claim 5, wherein information of wire capacitance andor inductance is extracted as the information of the parasitic element of the semiconductor circuit in the parasitic element extracting step, a value of the wire capacitance, of which the information is extracted from the layout of the semiconductor circuit, is set in the parasitic element extracting step to be higher than a value of the wire capacitance existing in the wiring area in which no dummy wire is arranged, and a value of the inductance, of which the information is extracted from the layout of the semiconductor circuit, is set in the parasitic element extracting step to be lower than a value of the inductance existing in the wiring area in which no dummy wire is arranged.
7. A parasitic element extracting method according to claim 5, wherein a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated in the dummy wiring assuming step according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set in the dummy wiring assuming step, and the circuit layout of the wiring area is assumed in the dummy wiring assuming step so as to increase the adjacent wire existence probabilities of the wires of the wiring area at equal rates.
8. A parasitic element extracting method according to claim 5, wherein a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated in the dummy wiring assuming step according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set in the dummy wiring assuming step, and the circuit layout of the wiring area is assumed in the dummy wiring assuming step so as to equally increase the adjacent wire existence probabilities of the wires of the wiring area to a fixed adjacent wire existence probability.