1. A semiconductor integrated circuit, comprising:
at least one second semiconductor chip configured to generate an internal voltage; and
a first semiconductor chip comprising:
a monitoring unit configured to monitor the internal voltage; and
a first pad configured to provide monitoring result information output from the monitoring unit to a test device.
2. The semiconductor integrated circuit of claim 1, wherein the second semiconductor chip comprises a plurality of semiconductor chips configured to generate and use respective internal voltages.
3. The semiconductor integrated circuit of claim 1, wherein the monitoring unit comprises a comparator configured to compare a reference voltage received from the test device with the internal voltage and output the monitoring result information corresponding to the comparison result.
4. The semiconductor integrated circuit of claim 3, wherein the first semiconductor chip further comprises a second pad configured to receive the reference voltage from the test device.
5. A semiconductor integrated circuit, comprising
at least one second semiconductor chip configured to generate different internal voltages and select the different internal voltages in response to an internal voltage select signal; and
a first semiconductor chip configured to generate the internal voltage select signal in response to at least one of an address and a command and monitor the selected internal voltage to output result information corresponding to the monitoring result.
6. The semiconductor integrated circuit of claim 5, wherein the second semiconductor chip comprises:
a plurality of internal voltage generation units configured to generate the different internal voltages, respectively; and
an internal voltage selection unit configured to select one of the different internal voltages in response to the internal voltage select signal and provide the selected internal voltage to the first semiconductor chip.
7. The semiconductor integrated circuit of claim 5, wherein the first semiconductor chip comprises:
a code combination unit configured to generate the internal voltage select signal through a combination using the at least one of an address and a command; and
a monitoring unit configured to monitor the selected internal voltage and generate the result information corresponding to the monitoring result.
8. The semiconductor integrated circuit of claim 7, wherein the first semiconductor chip further comprises;
a first pad configured to provide the result information to a test device; and
a second pad configured to receive a reference voltage from the test device.
9. The semiconductor integrated circuit of claim 8, wherein the monitoring unit comprises a comparator configured to compare the reference voltage with the selected internal voltage and output the result information corresponding to the comparison result.
10. The semiconductor integrated circuit of claim 6, wherein the second semiconductor chip further comprises a plurality of through chip vias (TCVs) formed to penetrate the second semiconductor chip, and
wherein the plurality of TCVs are configured to transmit the internal voltage select signal and the selected internal voltage between the first and second semiconductor chip.
11. A semiconductor integrated circuit, comprising
at least one slave chip configured to generate internal voltages and transmit the internal voltages through a plurality of through chip vias (TCVs) formed by penetrating the slave chip; and
a master chip configured to monitor the internal voltages and generate result information corresponding to the monitoring result.
12. The semiconductor integrated circuit of claim 11, wherein the slave chip comprises:
a plurality of internal voltage generation units configured to generate the internal voltages, respectively; and
an internal voltage selection unit configured to select one of the internal voltages in response to an internal voltage select signal and provide the selected internal voltage to the master chip in response to a chip select signal.
13. The semiconductor integrated circuit of claim 12, wherein the master chip comprises:
a code combination unit configured to generate the internal voltage select signal and the chip select signal in response to at least one of an address and a command and provide the internal voltage select signal and the chip select signal to the slave chip through the TCVs; and
a comparison unit configured to compare a reference voltage with the selected internal voltage provided from the slave chip and output the result information corresponding to the comparison result.
14. The semiconductor integrated circuit of claim 13, wherein the master chip further comprises:
a first pad configured to receive the reference voltage from a test device; and
a second pad configured to provide the result information to the test device.
15. The semiconductor integrated circuit of claim 13, wherein the master chip further comprises:
a plurality of internal voltage generation units configured to generate internal voltages, respectively; and
an internal voltage selection unit configured to select one of the internal voltages generated from the respective internal voltage generation units included in the master chip in response to the internal voltage select signal and provide the selected internal voltage to the comparison unit in response to the chip select signal.
16. A semiconductor integrated circuit, comprising:
a first semiconductor chip configured to be selectively connected to an external controller and a test device; and
a plurality of second semiconductor chips stacked with the first semiconductor chip and configured to generate internal voltages under a control of the first semiconductor chip,
wherein the first semiconductor chip comprises:
a first pad configured to exchange a first signal with the external controller during a normal mode and receive a reference voltage from the test device during a test mode;
a comparison unit configured to compare the reference voltage with the internal voltages provided from the second semiconductor chips during the test mode;
a second pad configured to provide an output signal of the comparison unit to the test device during the test mode and exchange a second signal with the external controller during the normal mode;
a first path selection unit configured to selectively connect the comparison unit to the first pad in response to a test mode signal; and
a second path selection unit configured to selectively connect the comparison unit to the second pad in response to the test mode signal.
17. The semiconductor integrated circuit of claim 16, wherein the first semiconductor chip further comprises a test mode control unit configured to generate the test mode signal through a combination using at least one of an address and a command.
18. A method for measuring an internal voltage of a semiconductor integrated circuit which includes a plurality of semiconductor chips configured to generate respective internal voltages and stacked vertically, the method comprising:
providing an internal voltage generated by a second semiconductor chip of the semiconductor chips to a first semiconductor chip of the semiconductor chips during a test mode; and
comparing the internal voltage provided from the second semiconductor chip to a reference voltage applied from a test device in the first semiconductor chip, and providing result information corresponding to the comparison result to the test device.
19. The method of claim 18, wherein the reference voltage is varied by a set level within a critical range in response to the result information.
20. The method of claim 18, wherein the providing of the internal voltage comprises:
transmitting control signals from the first semiconductor chip to the other semiconductor chips through a plurality of through chip vias (TCVs) to select the second semiconductor chip; and
transmitting the internal voltage generated by the second semiconductor chip to the first semiconductor chip through the TCVs.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method to remove heavy metals from contaminated water and hydrocarbons in a fractured well stratum, said method comprising: introducing into said stratum a proppant formulation that comprises solid proppant particulates associated with a contaminant removal component in a sufficient quantity to remove at least a portion of the heavy metal contaminants or other targeted contaminants in said contaminated fluids.
2. A method according to claim 1 wherein said removal component comprises second particulates comprising an ion exchange resin andor a molecular sieve that are physically blended with said solid proppant particulates in said proppant formulation.
3. A method as according to claim 1 wherein said proppant formulation comprises an insoluble coating on said proppant particulates.
4. A method according to claim 3 wherein said coating comprises said contaminant removal component which has at least one sulfonic acid moiety, carboxylic acid moiety, phenolic moiety, aminoacid moiety, glycolamine moiety, polyamine moiety, quaternary amine moiety, or polyhydroxylic moiety.
5. A method according to claim 3 wherein said contaminant removal component is a second discrete particulate solid that is bound to an outer surface of said proppant particulate with said coating.
6. A method according to claim 5 wherein said second discrete particulate solid is a natural molecular sieve.
7. A method according to claim 5 wherein said second discrete particulate solid is a synthetic molecular sieve.
8. A method according to claim 5 wherein said second discrete particulate solid is an ion exchange resin.
9. A method according to claim 1 wherein said removal component is disposed in pores found in a particulate proppant solid.
10. A method according to claim 1 wherein said particulate proppants comprise pores in which said removal component is disposed in at least a portion thereof.
11. A proppant formulation useful for removing heavy metals from water and hydrocarbons to be produced from a fractured oil and gas production well strata, said proppant formulation comprising: (a) a plurality of particulate proppant solids associated with (b) a contaminant removal component in sufficient quantity to remove at least a portion of heavy metal contaminants in water and hydrocarbons produced from the fractured well stratum.
12. A proppant formulation according to claim 11 wherein said contaminant removal component comprises ion exchange resin or molecular sieve particulates that are mixed with said particulate proppant solids in said proppant formulation.
13. A proppant formulation according to claim 11 wherein said particulate proppant solids comprise pores in which said removal component is disposed in at least a portion thereof.
14. A proppant formulation according to claim 11 wherein said proppant formulation comprises an insoluble proppant coating.
15. A proppant formulation according to claim 14 wherein said coating comprises the contaminant removal component which is a moiety selected from the group consisting of at least one sulfonic acid, carboxylic acid, phenolic, aminoacid, glycolamine, polyamine, quaternary amine, and polyhydroxylic compound.
16. A proppant formulation according to claim 11 wherein said contaminant removal component is a second discrete particulate solid that is bound to an outer surface of said proppant particulate with said coating.
17. A proppant formulation according to claim 16 wherein said second discrete particulate solid is a natural molecular sieve.
18. A proppant formulation according to claim 16 wherein said second discrete particulate solid is a synthetic molecular sieve.
19. A proppant formulation according to claim 16 wherein said second discrete particulate solid is an ion exchange resin.
20. A proppant formulation according to claim 11 wherein said contaminant removal component has a cation exchange capacity for removing normally radioactive heavy metals from said water and hydrocarbons.
21. A proppant formulation according to claim 11 wherein said contaminant removal component is an integral component of a structure of said proppant solids.
22. A proppant formulation according to claim 21 wherein said proppant solids are ceramic.
23. A proppant formulation according to claim 11 wherein said each proppant solid contains a solid core.
24. A proppant formulation according to claim 23 wherein said contaminant removal agent is integral with said solid core.
25. A method to remove heavy metals from contaminated water and hydrocarbons in a fractured well stratum, said method comprising: introducing into a well a gravel pack or filter sand bed solid particulates associated with a contaminant removal component in a sufficient quantity to remove at least a portion of the heavy metal contaminants in said contaminated water and hydrocarbons.
26. A gravel pack or filter sand formulation useful for removing heavy metals from water and hydrocarbons to be produced from a fractured oil and gas production well strata, said gravel pack or filter sand formulation comprising: (a) a plurality of particulate solids associated with (b) a contaminant removal component in sufficient quantity to remove at least a portion of heavy metal contaminants in water and hydrocarbons produced from the fractured well stratum.