1. A method for selectively reducing emissivity through a surface, the method comprising:
providing a low emissivity composite film, comprising:
a film substrate;
an underlayer of abrasion resistant hardcoat material coated on the film substrate and comprising a crosslinked acrylate polymer and metal oxide nanoparticles, the underlayer having a dried thickness of about 2 to about 6 microns and an abrasion delta haze of about 3 to about 5%; and
at least one infrared reflective layer;
a transparent protective top coat comprising a polysilazane, fluoro silane, fluoroalkyl silane, or combination thereof, wherein the protective top coat has a thickness of less than about 0.5 microns and is disposed over the infrared reflective layer;
wherein the composite film has an emissivity of less than about 0.30; and
wherein the underlayer is disposed between the film substrate and the infrared reflective layer; and
selectively positioning the low emissivity composite film relative to a generally planar surface so that either;
the low emissivity composite film is arranged in a first position generally coplanar with the surface to reduce emissivity through the surface; or
the low emissivity composite film is arranged in a second position generally non-coplanar with the surface to not reduce emissivity through the surface.
2. The method of claim 1 wherein the surface comprises an exterior surface of a window.
3. The method of claim 1 wherein the surface comprises an interior surface of a window.
4. The method of claim 1 wherein the surface comprises a surface of a skylight.
5. The method of claim 1 wherein the surface comprises a surface of a wall.
6. The method of claim 1 wherein the low emissivity film is only in proximity to the surface when in the first position.
7. The method of claim 6 wherein the low emissivity composite film is rolled when moved from the first to the second position.
8. The method of claim 1 wherein the low emissivity film is in proximity to the surface when in both the first position and the second position.
9. The method of claim 8 wherein the low emissivity film is adhered to a shade which is positioned in proximity to the generally planar surface.
10. The method of claim 8 wherein the low emissivity film is adhered to a blind which is positioned in proximity to the generally planar surface.
11. The method of claim 1 wherein the infrared reflecting layer comprises at least one core metallic layer selected from aluminum, copper, gold, nickel, silver, platinum, palladium, tungsten, titanium, and alloys thereof.
12. The method of claim 11 wherein the infrared reflecting layer further comprises at least one thin metal film having a thickness of about 1 to about 5 nm and comprising at least one metal selected from nickel, chromium, niobium, gold, platinum, cobalt, zinc, molybdenum, zirconium, vanadium, mixtures thereof, and alloys thereof.
13. The method of claim 12 wherein the thin metal film comprises a nickel-chromium alloy.
14. The method of claim 11 wherein the infrared reflective layer comprises at least one spacer layer comprising a transparent conductive layer, a dielectric layer, or combinations thereof.
15. The method of claim 1 wherein the infrared reflective layer comprises at least one transparent conductive layer comprising indium zinc oxide.
16. The method of claim 1, wherein the metal oxide nanoparticles have a particle size of 0.1 micron or less.
17. The method of claim 1, wherein the underlayer comprises about 21 to about 65 weight percent nanoparticles, based on the total weight of the hardcoat material.
18. The method of claim 1, wherein the metal oxide nanoparticles comprise silicon dioxide, aluminum oxide, or a combination thereof.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A frequency modulating path for generating a frequency modulated clock, comprising:
a direct feed input, arranged for directly modulating frequency of an oscillator; and
a compensating feed input, arranged for compensating effects of said frequency modulating on a phase error;
wherein said compensating feed input is resampled by a down-divided clock to produce a plurality of samples, said down-divided clock is an integer edge division of said oscillator, and said samples are further sampled by a frequency reference clock.
2. The frequency modulating path of claim 1, wherein a frequency of said down-divided clock is higher than a frequency of said compensating feed input.
3. The frequency modulating path of claim 1, wherein a sampling rate of said direct feed input is lower than a frequency of said down-divided clock.
4. The frequency modulating path of claim 1, wherein samples of said direct feed input are synchronous to said oscillator.
5. The frequency modulating path of claim 1, comprising:
a reference phase generator, comprising:
a resampling circuit, arranged for receiving said compensating feed input at a first clock, and resampling said compensating feed input by said down-divided clock to produce said samples;
a first accumulator, coupled to said resampling circuit, said first accumulator arranged for accumulating said samples according to said down-divided clock to generate a first accumulated result; and
a sampler, coupled to said first accumulator, said sampler arranged for sampling said first accumulated result according to said frequency reference clock, and accordingly generating a sampled result, wherein a reference phase output is updated according to at least said sampled result.
6. The frequency modulating path of claim 5, wherein said reference phase generator further comprises:
a second accumulator, arranged for receiving a channel frequency command word (FCW) input, and accumulating said channel FCW input according to said frequency reference clock to output a second accumulated result; and
an adder, coupled to said second accumulator and said sampler, said adder arranged for generating said reference phase output by adding said sampled result to said second accumulated result.
7. The frequency modulating path of claim 5, wherein said down-divided clock is synchronous with said first clock.
8. The frequency modulating path of claim 5, wherein a frequency of said down-divided clock is higher than a frequency of said first clock.
9. The frequency modulating path of claim 5, wherein said first clock is derived from dividing a frequency of said frequency modulated clock.
10. A reference phase generator for generating a reference phase output, comprising:
a resampling circuit, arranged for receiving a modulating frequency command word (FCW) input at a first clock, and resampling said modulating FCW input by a second clock to produce a plurality of samples;
a first accumulator, coupled to said resampling circuit, said first accumulator arranged for accumulating said samples according to said second clock to generate a first accumulated result; and
a sampler, coupled to said first accumulator, said sampler arranged for sampling said first accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein said reference phase output is updated according to at least said sampled result.
11. The reference phase generator of claim 10, further comprising:
a second accumulator, arranged for receiving a channel FCW input, and accumulating said channel FCW input according to said frequency reference clock to output a second accumulated result; and
an adder, coupled to said second accumulator and said sampler, said adder arranged for generating said reference phase output by adding said sampled result to said second accumulated result.
12. The reference phase generator of claim 10, wherein said second clock is synchronous with said first clock.
13. The reference phase generator of claim 10, wherein a frequency of said second clock is higher than a frequency of said first clock.
14. The reference phase generator of claim 10, wherein each of said first clock and said second clock is a down-divided clock derived from a frequency modulated clock.
15. A frequency modulating method for generating a frequency modulated clock, comprising:
utilizing a direct feed input for directly modulating frequency of an oscillator;
utilizing a compensating feed input for compensating effects of said frequency modulating on a phase error;
resampling said compensating feed input by a down-divided clock to produce a plurality of samples, wherein said down-divided clock is an integer edge division of said oscillator; and
sampling said samples by a frequency reference clock.
16. The frequency modulating method of claim 15, wherein a frequency of said down-divided clock is higher than a frequency of said compensating feed input.
17. The frequency modulating method of claim 15, wherein a sampling rate of said direct feed input is lower than a frequency of said down-divided clock.
18. The frequency modulating method of claim 15, wherein samples of said direct feed input are synchronous to said oscillator.
19. The frequency modulating method of claim 15, wherein
said resampling step comprises:
receiving said compensating feed input at a first clock, and resampling said compensating feed input by said down-divided clock to produce said samples; and
accumulating said samples according to said down-divided clock to generate a first accumulated result; and
said sampling step comprises:
sampling said first accumulated result according to said frequency reference clock, and accordingly generating a sampled result, wherein a reference phase output is updated according to at least said sampled result.
20. The frequency modulating method of claim 19, further comprising:
receiving a channel frequency command word (FCW) input, and accumulating said channel FCW input according to said frequency reference clock to output a second accumulated result; and
generating said reference phase output by adding said sampled result to said second accumulated result.
21. The frequency modulating method of claim 19, wherein said down-divided clock is synchronous with said first clock.
22. The frequency modulating method of claim 19, wherein a frequency of said down-divided clock is higher than a frequency of said first clock.
23. The frequency modulating method of claim 19, wherein said first clock is derived from dividing a frequency of said frequency modulated clock.
24. A method for generating a reference phase output, comprising:
receiving a modulating frequency command word (FCW) input at a first clock, and resampling said modulating FCW input by a second clock to produce a plurality of samples;
accumulating said samples according to said second clock to generate a first accumulated result; and
sampling said first accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein said reference phase output is updated according to at least said sampled result.
25. The method of claim 24, further comprising:
receiving a channel FCW input, and accumulating said channel FCW input according to said frequency reference clock to output a second accumulated result; and
generating said reference phase output by adding said sampled result to said second accumulated result.
26. The method of claim 24, wherein said second clock is synchronous with said first clock.
27. The method of claim 24, wherein a frequency of said second clock is higher than a frequency of said first clock.
28. The method of claim 24, wherein each of said first clock and said second clock is a down-divided clock derived from a frequency modulated clock.