1. A cluster resonator, comprising:
a first conducting plane;
a second substantially parallel conducting plane;
a cluster of vias of essentially uniform length oriented substantially normal to the conducting planes each via in the cluster comprising a first end and a second end;
a first conducting pad disposed in a third plane substantially parallel and capacitively coupled to the first conducting plane and physically coupled with the vias of the cluster of vias proximate their first ends; and
a second conducting pad disposed in a fourth plane substantially parallel and capacitively coupled to the second conducting plane and physically coupled with the vias of the cluster of vias proximate their second ends, wherein the vias are physically connected to only the first and second conducting pads; and
wherein a combined inductance and capacitance of the cluster of vias form an electromagnetically resonant shunt circuit between the first and second conducting planes; and
wherein the vias of the cluster of vias are disposed along a perimeter that defines an interior region and one or more interior vias are routed within the interior region of the cluster of vias; and
wherein the interior vias comprise portions of transmission lines passing electrical signals through the cluster resonator.
2. A cluster resonator, comprising:
a first conducting plane;
a second substantially parallel conducting plane;
a cluster of vias of essentially uniform length oriented substantially normal to the conducting planes, each via in the cluster comprising a first end and a second end;
a first conducting pad disposed in a third plane substantially parallel and capacitively coupled to the first conducting plane and physically coupled with the vias of the cluster of vias proximate their first ends; and
a second conducting pad disposed in a fourth plane substantially parallel and capacitively coupled to the second conducting plane and physically coupled with the vias of the cluster of vias proximate their second ends, wherein the vias are physically connected to only the first and second conducting pads; and
wherein the first or second conducting pad is external relative to the first and second conducting planes.
3. The cluster resonator of claim 1, wherein the first or second conducting pad is internal relative to the first and second conducting planes.
4. The cluster resonator of claim 1, wherein the first and second conducting pads are internal relative to the first and second conducting planes.
5. The cluster resonator of claim 1, wherein the first and second conducting pads are external relative to the first and second conducting planes.
6. The cluster resonator of claim 1 or 2, wherein its topology comprises a mechanically balanced structure.
7. The cluster resonator of claim 1 or 2, wherein the first and second conducting planes are metallic layers incorporated with a multi-layered panel circuit.
8. The cluster resonator of claim 7, wherein the multi-layered panel circuit is a multi-layered printed circuit board and the cluster resonator comprises an array of plated through holes.
9. The cluster resonator of claim 7, wherein the multi-layered panel circuit is a multi-chip module.
10. The cluster resonator of claim 7, wherein the multi-layered panel circuit is a semiconductor chip.
11. The cluster resonator of claim 1, wherein the cluster of vias is disposed along a circular path.
12. The cluster resonator of claim 1, wherein the cluster of vias is disposed along an elliptical path.
13. The cluster resonator of claim 1, wherein the cluster of vias is disposed along a polygonal path.
14. The cluster resonator of claim 1, wherein spacing of vias within the cluster of vias effects a Faraday cage that substantially shields the interior region from RF fields propagating within the first and second conducting planes.
15. The cluster resonator of claim 14, wherein spacing of the vias within the cluster of vias in relation to the interior vias effects a predetermined line impedance in the interior vias.
16. A cluster resonator, comprising:
a first conducting plane;
a second substantially parallel conducting plane;
a cluster of vias of essentially uniform length oriented substantially normal to the conducting planes, each via in the cluster comprising a first end and a second end;
first ends of each via in the cluster of vias coupled with the first conducting plane; and
a first conducting pad disposed in a third plane parallel and external to the region between the first and second conducting planes and capacitively coupled to the second conducting plane and physically coupled to each via in the cluster of vias proximate their second ends, wherein the vias in the cluster of vias are physically connected to only the first conducting plane and the first conducting pad.
17. The cluster resonator of claim 16, wherein a combined inductance and capacitance of the cluster of vias form an electromagnetically resonant shunt circuit between the first and second conducting planes.
18. The cluster resonator of claim 16, wherein the vias of the cluster of vias are disposed along a perimeter that defines an interior region.
19. The cluster resonator of claim 18, wherein one or more interior vias are routed within the internal region of the cluster of vias.
20. The cluster resonator of claim 19, wherein the interior vias comprise portions of transmission lines passing electrical signals through the resonant element.
21. The cluster resonator of claim 16 comprising a second cluster of vias, each via in the second cluster of vias comprising a first end and a second end, wherein the vias in the second cluster of vias are coupled proximate their first ends to the second conducting plane and proximate their second ends to a second conducting pad disposed in a fourth plane parallel and external to the region between the first and second conducting planes and capacitively coupled to the first conducting plane, wherein the vias in the cluster of vias are physically connected to only the second conducting plane and the second conducting pad.
22. The cluster resonator of claim 21 wherein its topology comprises a mechanically balanced structure.
23. The cluster resonator of claim 16, wherein the first and second conducting planes are metallic layers incorporated with a multi-layered panel circuit.
24. The cluster resonator of claim 23, wherein the multi-layered panel circuit is a multi-layered printed circuit board and the cluster resonator comprises an array of plated through holes.
25. The cluster resonator of claim 16, wherein the multi-layered panel circuit is a multi-chip module.
26. The cluster resonator of claim 16, wherein the multi-layered panel circuit is a semiconductor chip.
27. The cluster resonator of claim 18, wherein the cluster of vias is disposed along a circular path.
28. The cluster resonator of claim 18, wherein the cluster of vias is disposed along an elliptical path.
29. The cluster resonator of claim 18 wherein the cluster of vias is disposed along a polygonal path.
30. The cluster resonator of claim 19, wherein spacing of the vias of the cluster of vias effects a Faraday cage that substantially shields the interior region from RF fields propagating within the first and second conducting planes.
31. The cluster resonator of claim 30, wherein spacing of the vias of the cluster of vias in relation to the interior vias effects a predetermined line impedance in the interior vias.
32. The cluster resonator of claims 1 or 6, further comprising a plurality of resonant vias and associated first and second conducting pads disposed in a periodic array associated with the first and second conducting planes.
33. The cluster resonator of claim 16, further comprising a plurality of resonant vias and associated first conducting pads disposed in a periodic array associated with the first and second conducting planes.
34. The cluster resonator of claims 1 or 6, wherein a diameter of the vias of the cluster of vias is selected to effect a predetermined inductance.
35. The cluster resonator of claim 16, wherein a diameter of the vias of the cluster of vias is selected to effect a predetermined inductance.
36. A cluster resonator comprising:
a first conducting plane;
a second substantially parallel conducting plane;
a first conducting pad disposed in a third substantially parallel plane internal to the region between the first and second conducting planes;
a first cluster of vias oriented substantially normal to the first conducting plane and first conducting pad and disposed therebetween, each via of the cluster having a first end and a second end, wherein the first and second ends are physically connected respectively to the first conducting plane and first conducting pad; and
a second conducting pad disposed in a fourth substantially parallel plane internal to the region between the first and second conducting planes;
a second cluster of vias oriented substantially normal to the second conducting plane and second conducting pad and disposed therebetween, each via of the cluster having a first end and a second end, wherein the first and second ends are physically connected respectively to the second conducting plane and second conducting pad; and
wherein the first and second conducting pads are proximate and capacitively coupled to each other; and
wherein the vias of the clusters of vias are disposed along a common perimeter thereby forming substantially field free interior regions therewithin; and
wherein one or more electrically isolated interior vias traverse the interior regions of the clusters of vias, the interior vias comprising portions of transmission lines for passing electrical signals therethrough.
37. The cluster resonator of claim 36, wherein a spacing of the vias of the clusters of vias in relation to the interior vias is selected to effect a predetermined line impedance in the interior vias.
38. The cluster resonator of claim 36, wherein a diameter of the vias of the clusters of vias is selected to effect a predetermined inductance.
39. The cluster resonator of claim 36, wherein the common perimeter is circular.
40. The cluster resonator of claim 36, wherein the common perimeter is elliptical.
41. The cluster resonator of claim 36, wherein the common perimeter is polygonal.
42. The cluster resonator of claim 36, wherein the first and second conducting planes are metallic layers incorporated within a multi-layered panel circuit.
43. The cluster resonator of claim 42, wherein the multi-layered panel circuit is a multi-layered printed circuit board and the cluster resonator comprises an array of plated through holes.
44. The cluster resonator of claim 42, wherein the multi-layered panel circuit is a multi-chip module.
45. The cluster resonator of claim 42, wherein the multi-layered panel circuit is a semiconductor chip.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A variable delay circuit comprising:
a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal;
a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit;
a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increasedecrease signal; and
a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
2. The variable delay circuit of claim 1, wherein the input signal is a clock, and the second control unit controls the delay value of the non-selected delay unit to be N*clock (N is an integer of 2 or larger)\u2212the delay value of the selected delay unit.
3. The variable delay circuit of claim 2, wherein the selection signal generation unit generates a selection signal to change a delay unit selected at a time when a difference between the delay values of the first delay unit and the second delay unit becomes M*clock (M is an integer of 1 or larger).
4. The variable delay circuit of claim 1, wherein the first control unit includes a first charge pump that generates a first chargingdischarging current in response to the delay increasedecrease signal.
5. The variable delay circuit of claim 4, wherein the second control unit includes:
a total delay detector that receives the input signal and a signal obtained from the input signal passing through the first delay unit and the second delay unit and generates a control signal for controlling the delay value of the delay unit which is not selected by the selection signal; and
a second charge pump that generates a second chargingdischarging current in response to the control signal.
6. The variable delay circuit of claim 5, wherein the first delay unit includes:
a first selection unit configured to select one of the first chargingdischarging current and the second chargingdischarging current;
a first loop filter configured to be charged and discharged in response to an output of the first selection unit; and
a first voltage controlled delay line configured to delay an input signal to make an output in response to a voltage charged in the first loop filter.
7. The variable delay circuit of claim 6, wherein the second delay unit includes:
a second selection unit configured to select one of the first chargingdischarging current and the second chargingdischarging current;
a second loop filter configured to be charged and discharged in response to an output of the second selection unit; and
a second voltage controlled delay line configured to delay an input signal to make an output in response to an output voltage of the second loop filter.
8. The variable delay circuit of claim 5, wherein the delay circuit includes:
a third selection unit configured to input one of the input signal and the output signal of the second delay unit to the first delay unit in response to the selection signal;
a fourth selection unit configured to input one of the output signal of the first delay unit and the input signal to the second delay unit in response to the selection signal; and
a fifth selection unit configured to select one of the output signals of the first delay unit and the second delay unit as an output signal of the variable delay circuit in response to the selection signal and transmit the other signal to the second control unit.
9. A delay-locked loop comprising:
a variable delay unit that delays an external clock to output an internal clock;
a replica delay unit that delays the internal clock to generate a feedback clock; and
a phase comparison unit that compares a phase of the feedback clock with a phase of the external clock to generate a delay increasedecrease signal,
wherein the variable delay unit includes:
a delay circuit that includes a first delay unit and a second delay unit and delays the external signal to generate the internal signal;
a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the external signal from the first delay unit and the second delay unit;
a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increasedecrease signal; and
a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
10. The delay-locked loop of claim 9, wherein the second control unit controls the delay value of the non-selected delay unit to be N*clock (N is an integer of 2 or larger)\u2212the delay value of the selected delay unit.
11. The delay-locked loop of claim 10, wherein the selection signal generation unit generates a selection signal to change a delay unit selected at a time when a difference between the delay values of the first delay unit and the second delay unit becomes M*clock (M is an integer of 1 or larger).
12. The delay-locked loop of claim 11, wherein the first control unit includes:
a first charge pump that generates a first chargingdischarging current in response to the delay increasedecrease signal, and
the second control unit includes:
a total delay detector that receives the input signal and a signal obtained from the input signal passing through the first delay unit and the second delay unit and generates a control signal for controlling the delay value of the delay unit which is not selected by the selection signal; and
a second charge pump that generates a second chargingdischarging current in response to the control signal.
13. The delay-locked loop of claim 12, wherein the first delay unit includes:
a first selection unit configured to select one of the first chargingdischarging current and the second chargingdischarging current;
a first loop filter configured to be charged and discharged in response to an output of the first selection unit; and
a first voltage controlled delay line configured to delay an input signal to make an output in response to a voltage charged in the first loop filter, and
the second delay unit includes:
a second selection unit configured to select one of the first chargingdischarging current and the second chargingdischarging current;
a second loop filter configured to be charged and discharged in response to an output of the second selection unit; and
a second voltage controlled delay line configured to delay an input signal to make an output in response to an output voltage of the second loop filter.
14. The delay-locked loop of claim 12, wherein the delay circuit includes:
a third selection unit configured to input one of the input signal and the output signal of the second delay unit to the first delay unit in response to the selection signal;
a fourth selection unit configured to input one of the output signal of the first delay unit and the input signal to the second delay unit in response to the selection signal; and
a fifth selection unit configured to select one of the output signals of the first delay unit and the second delay unit as an output signal of the variable delay circuit in response to the selection signal and transmit the other signal to the second control unit.