1. Device for protecting an electrical circuit fed by an alternating current, comprising a housing and a fuse element disposed in the housing, wherein the housing comprises a first portion and a second portion which are mobile in relation to one another, and elastic means suitable for causing the first portion to bear against the second portion and causing the housing to be set in a closed state.
2. Device according to claim 1, in which the elastic means are implemented in such a way as to allow the separation of the first portion and the second portion of the housing when the pressure in the housing is greater than a threshold.
3. Device according to claim 1, comprising at least two connection terminals coupled on either side of the fuse element and fixed onto the second portion, the first and second portions being implemented in such a way that they become separated from one another according to the direction defined by the two connection terminals.
4. Device according to claim 1, wherein the first portion and the second portion of the housing comprise a material with a non-carbonizing surface on their inner surface.
5. Device according to claim 3, wherein the fuse element comprises at least one brazed joint implemented between the two connection terminals.
6. Electrical contactor comprising a switching element suitable for opening or closing an electrical circuit fed by an alternating current, and control means suitable for controlling the switching element to open or close the electrical circuit, characterised in that the switching element comprises a protection device according to claim 1.
7. Electrical contactor according to claim 6, further comprising electrical coupling terminals connected to said electrical circuit, the switching element comprises at least two connection studs connected respectively to the connection terminals of the protection device, and the control means comprise movement means coupled to the switching element and allowing the switching element to be moved between an open position of the electrical circuit where the connection studs are decoupled from the electrical coupling terminals and a closed position of the electrical circuit where the connection studs are coupled to the electrical coupling terminals.
8. Electrical contactor according to claim 7, further comprising elastic contact means coupled to the movement means in such a way as to bring the switching element to the closed position of the electrical circuit, the elastic contact means comprising said elastic means of the protection device.
9. Electrical contactor according to claim 6, in which the contactor is a power contactor.
10. Method for protecting an electrical circuit fed by an alternating current, comprising:
a) generating an electrical arc following the melting of a fuse element in a housing caused, the melting being caused by a current increase linked to a short circuit;
b) opening the housing;
c) expanding the electrical arc outside the housing;
d) closing the housing;
e) breaking the electrical arc when the housing closes;
f) repeating steps a) to e) if an electrical arc is reformed.
11. Method according to claim 10, in which the housing opens when the pressure in said housing is greater than a threshold and closes when said pressure is below the threshold, the pressure in said housing reducing when the absolute value of the alternating current reduces.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for facilitating load reordering through cacheline marking, the method comprising:
receiving a load to be executed;
determining whether a cacheline for the load has been load-marked by a thread which is performing the load;
if so, performing the load; and
if not,
obtaining the cacheline;
attempting to load-mark the cacheline; and
if the cacheline is successfully load-marked, performing the load.
2. The method of claim 1, wherein determining whether the cacheline for the load has been load-marked involves checking a private buffer associated with the thread.
3. The method of claim 1, wherein determining whether the cacheline for the load has been load-marked involves checking the load-mark on the cacheline to determine if it has been set by the thread.
4. The method of claim 2, wherein the private buffer for the thread maintains the addresses of the cachelines whose load-marks have been set by the thread.
5. The method of claim 4, wherein checking the private buffer for the thread involves checking the private buffer to see if the address of the cacheline exists in the private buffer.
6. The method of claim 1, wherein the load-mark for the cacheline includes a load counter which keeps a count of how many threads hold load-marks on the cacheline.
7. The method of claim 2, wherein load-marking the cacheline involves:
reading the load counter value from the cacheline;
incrementing the load counter value;
storing the incremented load counter value to the cacheline; and
adding a corresponding entry to the private buffer for the thread which includes the address of the cacheline.
8. The method of claim 2, wherein the method further comprises:
removing the load-mark from the cacheline; and
removing the address of the cacheline from the private buffer.
9. The method of claim 8, wherein removing the load-mark from the cacheline involves:
reading the load counter value from the cacheline;
decrementing the load counter value; and
storing the decremented load counter value to the cacheline.
10. The method of claim 1, wherein attempting to load-mark the cacheline involves:
determining if the cacheline has been store-marked by the thread;
if so, load-marking the cacheline; and
if not, determining if the cacheline has been store-marked by another thread;
if so, not load-marking of the cacheline; and
if not, load-marking the cacheline.
11. The method of claim 10, wherein determining if the cacheline has been store-marked by the thread involves checking a store-mark buffer, which maintains addresses of cachelines whose store-marks have been set by the thread, to see if the address of the cacheline exists in the store-mark buffer.
12. The method of claim 10, wherein determining if the cacheline has been store-marked by another thread involves:
checking a store-mark in a copy of the cacheline in a local cache to see if the store-mark has been set; and
if there is no valid copy of the cacheline in the local cache, using a cache-coherency mechanism to determine if the store-mark has been set in a copy of the cacheline in another cache or in memory.
13. The method of claim 12, wherein using the cache-coherence mechanism to determine if the store-mark has been set by another thread involves:
sending a cache-coherence signal to other caches andor the memory to determine whether a copy of the cacheline has been store-marked by another thread; and
if another copy of the cacheline has been store-marked by another thread, receiving a NACK signal.
14. The method of claim 1, wherein if the thread has load-marked the cacheline, no other thread can store to the cacheline.
15. The method of claim 1, wherein if the thread has load-marked the cacheline, no other thread can store-mark the cacheline.
16. The method of claim 1, wherein the method further comprises:
receiving a set of loads directed to a set of cachelines which are load-marked by the thread;
reordering the set of loads into a new order; and
performing the set of loads in the new order.
17. The method of claim 16, wherein the set of loads that are performed in the new order appear to other threads to have been performed in program order.
18. An apparatus that facilitates load reordering through cacheline marking, comprising:
a receiving mechanism configured to receive a load to be executed;
a determination mechanism configured to determine whether a cacheline for the load has been load-marked by a thread which is performing the load;
an execution mechanism configured to perform the load if the cacheline has been load-marked;
a load-marking mechanism configured to load-mark the cacheline if the cacheline has not been load-marked;
wherein if the cacheline has not been load-marked, the determination mechanism is configured to:
obtain the cacheline; and to
attempt to load-mark the cacheline.
19. The apparatus of claim 18, wherein the determination mechanism is configured to check a private buffer associated with the thread.
20. The apparatus of claim 18, wherein the determination mechanism is configured to check the load-mark on the cacheline to determine if it has been set by the thread.
21. The apparatus of claim 19, wherein the private buffer for the thread maintains the addresses of the cachelines whose load-marks have been set by the thread.
22. The apparatus of claim 18, wherein the load-mark for the cacheline includes a load counter which keeps a count of how many threads hold load-marks on the cacheline.
23. The apparatus of claim 19, wherein the load-marking mechanism is configured to:
read the load counter value from the cacheline;
increment the load counter value;
store the incremented load counter value to the cacheline; and to
add a corresponding entry to the private buffer for the thread which includes the address of the cacheline.
24. The apparatus of claim 19, further comprising a removal mechanism configured to:
remove the load-mark from the cacheline; and to
remove the address of the cacheline from the private buffer.
25. The apparatus of claim 24, wherein the removal mechanism is further configured to:
read the load counter value from the cacheline;
decrement the load counter value; and to
store the decremented load counter value to the cacheline.
26. The apparatus of claim 18, wherein while attempting to load-mark the cacheline, the determination mechanism is configured to:
determine if the cacheline has been store-marked by the thread;
if so, to load-mark the cacheline; and
if not, to determine if the cacheline has been store-marked by another thread;
if so, to not load-marking of the cacheline; and
if not, to load-mark the cacheline.
27. The apparatus of claim 18, further comprising:
a receiving mechanism configured to receive a set of loads directed to a set of cachelines which are load-marked by the thread;
a reordering mechanism configured to reorder the set of loads into a new order; and
wherein the execution mechanism is configured to perform the set of loads in the new order.
28. A computer system that facilitates load reordering through cacheline marking, comprising:
a processor;
a memory;
a receiving mechanism configured to receive a load to be executed;
a determination mechanism configured to determine whether a cacheline for the load has been load-marked by a thread which is performing the load;
an execution mechanism configured to perform the load if the cacheline has been load-marked;
a load-marking mechanism configured to load-mark the cacheline if the cacheline has not been load-marked;
wherein if the cacheline has not been load-marked, the determination mechanism is configured to:
obtain the cacheline; and to
attempt to load-mark the cacheline.