1. A circuit for driving an electroluminescent device, comprising:
a controller configured to determine whether a gray scale of input video data is greater than a reference value and configured to add first dummy bit data or second dummy bit data to the first video data, depending on the gray scale of the input video data, to thereby generate second video data; and
a data driver configured to generate data signals corresponding to the first video data using a method corresponding to the dummy bit data included in the generated second video data.
2. The circuit of claim 1, wherein the first dummy bit data have a different logic value from the second dummy bit data.
3. The circuit of claim 1, wherein the data driver comprises:
a first signal generating circuit configured to generate data signals having an amplitude corresponding to the first video data when the dummy bit data included in the generated second video data are the first dummy bit data; and
a second signal generating circuit configured to generate substantially constant amplitude signals during a period of time that corresponds to the first video data when the dummy bit data included in the generated second video data are the second dummy bit data.
4. The circuit of claim 1, wherein the first dummy bit data are added to the first video data when a gray scale value of the first video data is greater than the reference value.
5. The circuit of claim 1, wherein the second dummy bit data are added to the first video data when a gray scale value of the first video data is less than the reference value.
6. The circuit of claim 1, wherein the controller includes a register for storing the reference value.
7. An organic electroluminescent display device incorporating the circuit of claim 1.
8. The circuit of claim 1, wherein the first dummy data bit or the second dummy data bit is provided at an end of the first video signal to generate the second video data.
9. The circuit of claim 1, wherein the first dummy bit data comprises a logical \u20181\u2019 bit or a logical \u20180\u2019 bit.
10. A circuit for driving an electroluminescent device, comprising:
a controller that receives a first video signal and that outputs a second video signal based on a gray scale of the first video signal, wherein the first video signal is different from the second video signal, and wherein the controller is configured to add dummy bit data to the first video signal to thereby generate the second video signal, and wherein the dummy bit data is indicative of a gray scale level of the first video signal; and
a data driver that outputs data signals based on the second video signal.
11. The circuit of claim 10, wherein the data driver is configured to output data signals according to a first driving method when the gray scale of the first video signal is greater than a reference value, and wherein the data driver is configured to output data signals according to a second driving method when the gray scale of the first video signal is less than the reference value.
12. The circuit of claim 11, wherein the first driving method is a pulse amplitude modulation method.
13. The circuit of claim 12, wherein the second driving method is a pulse width modulation method.
14. The circuit of claim 11, wherein the second driving method is a pulse width modulation method.
15. The circuit of claim 10, wherein the data driver outputs data signals according to a first method when the dummy bit data in the second video signal indicates that the gray scale level of the first video signal is greater than a reference value, and wherein the data driver outputs data signals according to a second method when the dummy bit data in the second video signal indicates that the gray scale level of the first video signal is less than the reference value.
16. The circuit of claim 15, wherein the first method is a pulse amplitude modulation method, and wherein the second method is a pulse width modulation method.
17. An organic electroluminescent display device comprising the circuit of claim 10.
18. The circuit of claim 10, wherein the dummy bit data comprises a logical \u20181\u2019 bit or a logical \u20180\u2019 bit.
19. An electroluminescent device, comprising:
a plurality of data lines in a first direction;
a plurality of scan lines in a second direction, the first direction being different from the second direction;
a plurality of sub-pixels, each sub-pixel including a corresponding data line and a corresponding scan line;
a scan driver coupled to the plurality of scan lines;
a controller configured to receive input video data and to determine whether a gray scale level of the input video data is greater than a reference value or less than the reference value; and
a data driver coupled to the plurality of data lines, the data driver comprising:
a first signal generating circuit configured to drive the device using a first driving method, and
a second signal generating circuit configured to drive the device using a second driving method, wherein the first driving method is different from the second driving method, wherein the data driver is configured to receive signals from the controller that indicate a gray scale level of the input video data, and wherein the data driver is configured to cause either the first signal generating circuit or the second signal generating circuit to drive the electroluminescent device depending on the gray scale level of the input video data.
20. The electroluminescent device of claim 19, wherein the first signal generating circuit is configured to drive the device using a pulse amplitude modulation (PAM) method.
21. The electroluminescent device of claim 19, wherein the second signal generating circuit is configured to drive the device using a pulse width modulation (PWM) method.
22. The electroluminescent device of claim 19, wherein the controller is configured to add data to the input video data to generate one of first video data and second video data based on the input video data, at least one of the first video data or the second video data being different from the input video data, and wherein the added data is indicative of the gray scale level of the input video data.
23. The electroluminescent device of claim 22, wherein the first video data is different from the second video data.
24. The electroluminescent device of claim 22, wherein the data driver is configured to read the data added to the input video data, and wherein the data driver is configured to cause either the first signal generating circuit or the second signal generating circuit to drive the device, depending on the gray scale level of the input video data as reflected in the added data.
25. The electroluminescent device of claim 19, wherein each of the plurality of sub-pixels includes an organic electroluminescent layer for light emission.
26. The electroluminescent device of claim 19, wherein the first driving method is used when the gray scale of the input video data is greater than a reference value, and wherein the second driving method is used when the gray scale of the input video data is less than the reference value.
27. A method of driving an electroluminescent device, comprising:
detecting a gray scale level of input video data;
generating second video data based on the input video data;
driving the electroluminescent device using a first driving method when the gray scale level of the input video data is greater than a reference value; and
driving the electroluminescent device using a second driving method when the gray scale level of the input video data is less than the reference value, wherein driving the electroluminescent device using the first driving method includes generating data signals having an amplitude corresponding to the input video data when a dummy bit data included in the generated second video data are first dummy bit data, and wherein driving the electroluminescent device using the second driving method includes generating substantially constant amplitude signals during a period of time that corresponds to the input video data when a dummy bit data included in the generated second video data are second dummy bit data.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit representation analysis and verification data propagation system comprising:
a first data structure for storing a first plurality of search target data;
a second data structure for storing a circuit representation;
a first processing sequence for locating a search target within said second data structure;
a second processing sequence for:
selecting a first circuit entity in said circuit representation in said second data structure; and
determining verification data locations in said first circuit entity for placement of verification data based upon relationships of one or more said first plurality of search target data to one or more elements within the circuit representation which are related to said first circuit entity;
a third processing sequence for creating a second circuit entity which comprises a plurality of related circuit elements within said second data structure and verification data placed in said verification data locations; and
a fourth processing sequence for storing said circuit entities in said second data structure.
2. The system of claim 1, wherein said first circuit entity and second circuit entity each comprise a plurality of circuit elements.
3. The system of claim 1, wherein said plurality of circuit elements of said second circuit entity further comprises one or more circuit elements from within said second data structure and verification data placed in said verification data locations as determined by said second processing sequence.
4. The system of claim 1, wherein verification data placed in said verification data locations comprises first verification data identifiers which replaced circuit element identifiers initially stored in said second data structure as well as second verification data identifiers which were added to said second circuit entity.
5. The system of claim 1, wherein said first plurality of search target data comprises one or more circuit representation entities, nets, marker property data or model and port combinations which may be found in said second data structure.
6. The system of claim 1, further comprising:
a fourth data structure which stores a second plurality of search targets, each search target comprises a set of related element identifiers which may be found in a circuit representation stored in said second data structure;
a fifth processing sequence for determining if a said verification location data has circuit elements which match one or more search targets within second plurality of search targets; and
a fifth data structure which comprises one or more other processing sequences which are to be executed in place of the third processing sequence if a match is found between circuit elements of a said verification location and said second plurality of search targets.
7. The system of claim 1, further comprising a processing sequence which provides an error message or perform another specified action based upon a failure of a processing sequence to locate a specific search target within said second data structure.
8. The system of claim 1, wherein said interconnective pathways comprise a net.
9. The system of claim 1, wherein search targets comprise one or more net, port, cell, instance, model identifier or combination of one or more nets, ports, instances, cells or model identifiers which are found in said circuit representation.
10. The system of claim 1, wherein said circuit representation is a hierarchical netlist.
11. The system of claim 1, further comprising:
a fifth processing sequence that determines if said second circuit entity has been previously stored; and
a sixth processing sequence which aborts the fourth processing sequence and continues processing if said fifth processing sequence determines if said second circuit entity has previously been stored in said second data structure.
12. The system of claim 1, further comprising:
a fifth processing sequence which creates a change identifier which indicates the changes which were specified by the second processing sequence, wherein said changes describe the change or addition that was identified by verification data location and the applicable verification data which is to be placed in said location in said second circuit entity; and
a fifth processing sequence for creating an identifier for said second circuit entity which comprises a first circuit entity name for said selected first circuit entity coupled with said change identifier.
13. A circuit representation analysis and verification data propagation system comprising:
a first data structure for storing a first plurality of search target data;
a second data structure for storing a first circuit representation;
a third data structure for storing a second circuit representation;
a first processing sequence for locating a search target within said second data structure;
a second processing sequence for analyzing said first circuit representation in said second data structure by determining verification data locations for placement of verification data in said first circuit representation based upon relationships of one or more said search target data to one or more elements within the first circuit representation;
a third processing sequence for creating one or more circuit entities which describe combinations of a plurality of circuit elements within said second data structure with verification data placed in said verification data locations; and
a fourth processing sequence for storing said circuit entities in said third data structure.
14. The system of claim 13, wherein said first plurality of search target data comprises one or more net or marker data which may be found in said second data structure.
15. The system of claim 13, wherein search targets comprise one or more net, port, cell, instance, model identifier or combination of one or more nets, ports, instances, cells or model identifiers which is found in said first circuit representation.
16. The system of claim 13, further comprising:
a fourth data structure which stores a second plurality of search targets, each search target comprises a set of related element identifiers which may be found in a first circuit representation stored in said second data structure;
a fifth processing sequence for determining if said verification location data has circuit elements which match one or more search targets within second plurality of search targets; and
a sixth data structure which comprises one or more processing sequences which are to be executed if a match between circuit elements of a said verification location and said second plurality of search targets.
17. The system of claim 13, further comprising a fourth processing sequence which provides an error message or perform another specified action based upon a failure of a processing sequence to locate a specific search target within said second data structure.
18. The system of claim 13, wherein said second processing sequence determination of verification data locations further comprises placing a first verification data at a location wherein a circuit attribute or element associated with a critical data location matches a pattern or selection criteria associated with a critical circuit attribute data stored in said first data structure, said first verification data is associated with said critical circuit attribute.
19. The system of claim 13, wherein said first circuit representation is a hierarchical netlist.