1. A semiconductor device comprising:
a first semiconductor layer disposed over and above a substrate;
a second semiconductor layer disposed over and above the first semiconductor layer;
a gate recess disposed, through removal of a part of or all the second semiconductor layer, in a predetermined region over and above the first semiconductor layer;
an insulating film disposed over the gate recess and the second semiconductor layer;
a gate electrode disposed over the gate recess with the insulating film therebetween; and
a source electrode and a drain electrode disposed over and above the first semiconductor layer or the second semiconductor layer,
whereby a central portion of the gate recess is higher than peripheral portions of the gate recess along each sidewall of the gate recess, and
a bottom of the gate recess is below a bottom surface of each of the source electrode and the drain electrode,
wherein in the bottom of the gate recess, the insulating film directly contacts the first semiconductor layer at the peripheral portions.
2. A semiconductor device comprising:
a first semiconductor layer disposed over a substrate;
a second semiconductor layer disposed over the first semiconductor layer;
a third semiconductor layer disposed over the second semiconductor layer;
a gate recess disposed, through removal of all the third semiconductor layer and a part of or all the second semiconductor layer, in a predetermined region over the first semiconductor layer;
an insulating film disposed over the gate recess and the third semiconductor layer;
a gate electrode disposed over the gate recess with the insulating film therebetween; and
a source electrode and a drain electrode disposed over the first semiconductor layer or the second semiconductor layer,
whereby a central portion of the gate recess is higher than peripheral portions of the gate recess along each sidewall of the gate recess, and
a bottom of the gate recess is below a bottom surface of each of the source electrode and the drain electrode,
wherein in the bottom of the gate recess, the insulating film directly contacts the first semiconductor layer at the peripheral portions.
3. The semiconductor device according to claim 2,
wherein the third semiconductor layer comprises n-GaN.
4. The semiconductor device according to claim 1,
wherein the first semiconductor layer and the second semiconductor layer are formed from a nitride semiconductor.
5. The semiconductor device according to claim 1,
wherein the first semiconductor layer comprises i-GaN.
6. The semiconductor device according to claim 1,
wherein the second semiconductor layer comprises any one of AlGaN or InAlN.
7. A semiconductor device comprising:
a first semiconductor layer disposed over and above a substrate;
a second semiconductor layer disposed over and above the first semiconductor layer;
a gate recess disposed, through removal of a part of or all the second semiconductor layer, in a predetermined region over and above the first semiconductor layer;
an insulating film disposed over the gate recess and the second semiconductor layer;
a gate electrode disposed over the gate recess with the insulating film therebetween; and
a source electrode and a drain electrode disposed over and above the first semiconductor layer or the second semiconductor layer,
whereby a central portion of the gate recess is higher than peripheral portions of the gate recess along each sidewall of the gate recess, and
a bottom of the gate recess is below a bottom surface of each of the source electrode and the drain electrode,
wherein a third semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer,
wherein in the bottom of the gate recess, the insulating film directly contacts the third semiconductor layer at any one of the central portion, the peripheral portions, and both the central portion and the peripheral portions.
8. The semiconductor device according to claim 7,
wherein both the second semiconductor layer and the third semiconductor layer comprise AlGaN, and
the composition ratio of Al in the third semiconductor layer is lower than that in the second semiconductor layer.
9. The semiconductor device according to claim 1,
wherein the insulating film is formed from at least one material selected from the group consisting of oxides, nitrides, and oxynitrides of Si, Al, Hf, Zr, Ti, Ta, and W.
10. The semiconductor device according to claim 1,
wherein the semiconductor device is HEMT.
11. A semiconductor device comprising:
a first semiconductor layer disposed over a substrate;
a second semiconductor layer disposed over the first semiconductor layer;
a third semiconductor layer disposed over the second semiconductor layer;
a gate recess disposed, through removal of all the third semiconductor layer and a part of or all the second semiconductor layer, in a predetermined region over the first semiconductor layer;
an insulating film disposed over the gate recess;
a gate electrode disposed over the gate recess with the insulating film therebetween; and
a source electrode and a drain electrode disposed over the first semiconductor layer or the second semiconductor layer,
whereby a central portion of the gate recess is higher than peripheral portions of the gate recess along each sidewall of the gate recess, and
a bottom of the gate recess is below a bottom surface of each of the source electrode and the drain electrode,
wherein a fourth semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer,
wherein in the bottom of the gate recess, the insulating film directly contacts the fourth semiconductor layer at any one of the central portion, the peripheral portions, and both the central portion and the peripheral portions.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
generating at an ingress routing bridge in a TRansparent Interconnection of Lots of Links (TRILL) network, a trace message for a specified flow along a path from the ingress routing bridge to a destination reachable through the TRILL network;
transmitting the trace message from the ingress routing bridge to a next-hop routing bridge in the TRILL network;
receiving at the ingress routing bridge, a plurality of reply messages from routing bridges in response to transmitting said trace message; and
chaining said plurality of reply messages together to formulate said path and identify the routing bridges in said path and a location of any fault in said path;
wherein each of said plurality of reply messages comprises a TRILL header, identification of an ingress port and egress port at a routing bridge transmitting the reply message, a next-hop routing bridge identifier, and a hop count contained in an Operations, Administration, and Maintenance (OAM) field, the reply message transmitted based on a lookup in a forwarding information base at the routing bridge.
2. The method of claim 1 wherein generating said trace message comprises setting a bit in a TRILL header to identify said trace message as an Operations, Administration, and Maintenance (OAM) packet.
3. The method of claim 1 wherein generating said trace message comprises setting a time-to-live in a TRILL header to one.
4. The method of claim 1 wherein said trace message comprises a hop count and an identifier of the ingress routing bridge transmitting said trace message.
5. The method of claim 1 wherein the next-hop routing bridge is configured to update said trace message and forward said updated trace message to its next-hop routing bridge.
6. The method of claim 1 wherein said plurality of reply messages are received from the routing bridges in said path.
7. An apparatus comprising:
a processor for generating a trace message for a specified flow along a path from the apparatus to a destination reachable through a TRansparent Interconnection of Lots of Links (TRILL) network, transmitting the trace message to a next-hop routing bridge in the TRILL network, receiving a plurality of reply messages in response to transmitting said trace message, and chaining said plurality of reply messages together to formulate said path and identify routing bridges in said path and a location of any fault in said path; and
memory for storing path information received in said plurality of reply messages;
wherein each of said plurality of reply messages comprises a TRILL header, identification of an ingress port and egress port at a routing bridge transmitting the reply message, a next-hop routing bridge identifier, and a hop count contained in an Operations, Administration, and Maintenance (OAM) field, the reply message transmitted based on a lookup in a forwarding information base at the routing bridge.
8. The apparatus of claim 7 wherein said trace message comprises a bit set in a TRILL header to identify said trace message as an OAM packet.
9. The apparatus of claim 7 wherein a time-to-live in said trace message is set to one.
10. The apparatus of claim 7 wherein said trace message comprises a hop count and an identifier of the ingress routing bridge transmitting said trace message.
11. A routing bridge comprising:
a processor for receiving a trace message for a specified flow along a path from an ingress routing bridge to a destination reachable through a TRansparent Interconnection of Lots of Links (TRILL) network, performing a lookup in a forwarding information base to identify a next-hop routing bridge, transmitting a reply message to the ingress routing bridge, updating said trace message, and forwarding said updated trace message to a next-hop routing bridge; and
memory for storing the forwarding information base;
wherein the trace message comprises hop count and an identifier of the ingress routing bridge transmitting said trace message;
wherein the ingress routing bridge is operable to identify a location of any fault in said path based on the reply message;
wherein the reply message comprises, a TRILL header, identification of an ingress port and egress port at the routing bridge transmitting the reply message, the next-hop routing bridge identifier, and Operations, Administration, and Maintenance (OAM) field.
12. The routing bridge of claim 11 wherein said trace message comprises a bit set in a TRILL header to identify said trace message as an OAM packet.
13. The routing bridge of claim 11 wherein a time-to-live in said trace message is set to one.