1. A solid-electrolyte battery comprising a positive-electrode layer, a negative-electrode layer, and a solid-electrolyte layer that conducts lithium ions between the electrode layers, wherein
a buffer layer that is a LiNbO3 film is disposed between a positive-electrode active material and a solid electrolyte, and
a composition ratio (LiNb) of Li to Nb in the LiNbO3 film satisfies 0.93\u2266LiNb\u22660.98.
2. The solid-electrolyte battery according to claim 1, wherein the buffer layer is disposed between the positive-electrode layer and the solid-electrolyte layer.
3. The solid-electrolyte battery according to claim 1, wherein the buffer layer is disposed on a surface of a particle of the positive-electrode active material.
4. The solid-electrolyte battery according to claim 1, wherein the buffer layer has a thickness of 2 nm to 1 \u03bcm.
5. The solid-electrolyte battery according to claim 2, wherein the buffer layer has a thickness of 2 nm to 1 \u03bcm.
6. The solid-electrolyte battery according to claim 3, wherein the buffer layer has a thickness of 2 nm to 1 \u03bcm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed as new and desired to be protected by Letters Patent of the United States is:
1. A memory device comprising:
a plurality of first circuits, each first circuit having a first input for receiving a first clock signal and a second input for receiving a respective first input signal, each first circuit being controllable to latch its respective first input signal such that the first input signal has a data envelope corresponding to N number of cycles of the first clock signal, where N>1, each first circuit having at least one first output signal corresponding to the latched first input signal; and
a re-timing circuit coupled to said plurality of first circuits, said re-timing circuit having a third input for receiving a second clock signal, said re-timing circuit receiving said at least one first output signal from said first circuits and outputting re-timed first output signals in accordance with transitions of the second clock signal.
2. The memory device of claim 1, wherein each first circuit has two first output signals, a first one of said first output signals corresponding to the latched first input signal associated with a first edge of the first clock signal and a second one of said first output signals corresponding to the latched first input signal associated with a second edge of the first clock signal.
3. The memory device of claim 2, wherein said re-timing circuit receives said two first output signals from each of said first circuits and combines said first output signals into said re-timed first output signals.
4. The memory device of claim 1, further comprising:
a second circuit having a fourth input for receiving the first clock signal and a fifth input for receiving a second input signal, said second circuit being controllable to latch the second input signal such that the second input signal has a data envelope corresponding to N number of cycles of the first clock signal, where N>1, said second circuit having at least one second output signal corresponding to the latched second input signal,
wherein said re-timing circuit receives said at least one second output signal from said second circuit and uses said least one second output signal to re-time said first output signals.
5. The memory device of claim 4, wherein said second circuit has two second output signals, a first one of said second output signals corresponding to the latched second input signal associated with a first edge of the first clock signal and a second one of said second output signals corresponding to the latched second input signal associated with a second edge of the first clock signal.
6. The memory device of claim 4, wherein said second circuit has three second output signals, a first one of said second output signals corresponding to the latched second input signal associated with a first edge of the first clock signal, a second one of said second output signals corresponding to the latched second input signal associated with a second edge of the first clock signal and a third one of said second output signals corresponding to a synchronization signal associated with the first clock signal.
7. The memory device of claim 6, wherein said re-timing circuit comprises:
a reset circuit for generating a synchronization request signal, said reset circuit coupled to said third one of said second output signals and the second clock signal, said reset circuit outputting said synchronization request signal based on said third one of said second output signals;
a selection circuit for generating at least one selection signal responsive to said synchronization request signal; and
a data generator receiving said at least one selection signal and said first and second output signals and generating said re-timed first output signals responsive to said at least one selection signal.
8. The memory device of claim 7, wherein said data generator generates and outputs a re-timed first one of said second output signals and a re-timed second one of said second output signals.
9. The memory device of claim 1, wherein N is three.
10. The memory device of claim 1, wherein the first clock signal is received through a delay element and the second clock signal is generated based on said first clock signal.
11. The memory device of claim 1, wherein all of said latched first input signals remains valid for a period sufficiently long enough so that said re-timing circuit can output said re-timed first output signals regardless of voltage variations effecting a timing of said first circuits and said re-timing circuits.
12. The memory device of claim 1, wherein all of said latched first input signals remains valid for a period sufficiently long enough so that said re-timing circuit can output said re-timed first output signals regardless of temperature variations effecting a timing of said first circuits and said re-timing circuits.
13. A memory device comprising:
data capture circuitry for capturing and latching a plurality of input data signals responsive to a first clock signal, said data capture circuit outputting a plurality of captured data signals;
a first circuit for generating a plurality of synchronization signals responsive to the first clock signal, said synchronization signals simulating a timing of some of the plurality of input data signals; and
a second circuit responsive to a second clock signal, said second circuit receiving said plurality of synchronization signals and re-timing said captured data signals to be aligned with said second clock signal based on said synchronization signals.
14. The memory device of claim 13, wherein said first circuit is controllable by first and second clock edge selection signals such that some of said plurality of synchronization signals are aligned with a first transition of the first clock signal and the remaining of said plurality of synchronization signals are aligned with a second transition of the first clock signal.
15. The memory device of claim 13, wherein said data capture circuit comprises:
a plurality of first latch circuits, each first latch circuit having a first input for receiving the first clock signal and a second input for receiving respective input data signals, each first latch circuit being controllable to latch its respective input data signals such that the latched input data signals have a data envelope corresponding to N number of cycles of the first clock signal, where N>1.
16. The memory device of claim 15, wherein N is three.
17. The memory device of claim 13, wherein said second circuit comprises:
a reset circuit for generating a synchronization request signal, said reset circuit coupled to said synchronization signals and the second clock signal, said reset circuit outputting said synchronization request signal based on a timing of said synchronization signals with respect to the second clock signal;
a selection circuit for generating at least one selection signal responsive to said synchronization request signal; and
a data generator receiving said at least one selection signal and said captured data signals and re-timing said captured data signals to be aligned with said second clock signal responsive to said at least one selection signal.
18. A processor system comprising:
a processor; and
memory device coupled to said processor, said memory device comprising:
a plurality of first circuits, each first circuit having a first input for receiving a first clock signal and a second input for receiving a respective first input signal, each first circuit being controllable to latch its respective first input signal such that the first input signal has a data envelope corresponding to N number of cycles of the first clock signal, where N>1, each first circuit having at least one first output signal corresponding to the latched first input signal; and
a re-timing circuit coupled to said plurality of first circuits, said re-timing circuit having a third input for receiving a second clock signal, said re-timing circuit receiving said at least one first output signal from said first circuits and outputting re-timed first output signals in accordance with transitions of the second clock signal.
19. The system of claim 18, wherein each first circuit has two first output signals, a first one of said first output signals corresponding to the latched first input signal associated with a first edge of the first clock signal and a second one of said first output signals corresponding to the latched first input signal associated with a second edge of the first clock signal.
20. The system of claim 19, wherein said re-timing circuit receives said two first output signals from each of said first circuits and combines said first output signals into said re-timed first output signals.
21. The system of claim 18, wherein said memory device further comprises:
a second circuit having a fourth input for receiving the first clock signal and a fifth input for receiving a second input signal, said second circuit being controllable to latch the second input signal such that the second input signal has a data envelope corresponding to N number of cycles of the first clock signal, where N>1, said second circuit having at least one second output signal corresponding to the latched second input signal,
wherein said re-timing circuit receives said at least one second output signal from said second circuit and uses said least one second output signal to re-time said first output signals.
22. The system of claim 21, wherein said second circuit has two second output signals, a first one of said second output signals corresponding to the latched second input signal associated with a first edge of the first clock signal and a second one of said second output signals corresponding to the latched second input signal associated with a second edge of the first clock signal.
23. The system of claim 21, wherein said second circuit has three second output signals, a first one of said second output signals corresponding to the latched second input signal associated with a first edge of the first clock signal, a second one of said second output signals corresponding to the latched second input signal associated with a second edge of the first clock signal and a third one of said second output signals corresponding to a synchronization signal associated with the first clock signal.
24. The system of claim 23, wherein said re-timing circuit comprises:
a reset circuit for generating a synchronization request signal, said reset circuit coupled to said third one of said second output signals and the second clock signal, said reset circuit outputting said synchronization request signal based on said third one of said second output signals;
a selection circuit for generating at least one selection signal responsive to said synchronization request signal; and
a data generator receiving said at least one selection signal and said first and second output signals and generating said re-timed first output signals responsive to said at least one selection signal.
25. The system of claim 24, wherein said data generator generates and outputs a re-timed first one of said second output signals and a re-timed second one of said second output signals.
26. The system of claim 18, wherein N is three.
27. The system of claim 18, wherein the first clock signal is received through a delay element and the second clock signal is generated based on said first clock signal.
28. The system of claim 18, wherein all of said latched first input signals remains valid for a period sufficiently long enough so that said re-timing circuit can output said re-timed first output signals regardless of voltage variations effecting a timing of said first circuits and said re-timing circuits.
29. The system of claim 18, wherein all of said latched first input signals remains valid for a period sufficiently long enough so that said re-timing circuit can output said re-timed first output signals regardless of temperature variations effecting a timing of said first circuits and said re-timing circuits.
30. A processor system comprising:
a processor; and
a memory device connected to said processor, said memory device comprising:
data capture circuitry for capturing and latching a plurality of input data signals responsive to a first clock signal, said data capture circuit outputting a plurality of captured data signals;
a first circuit for generating a plurality of synchronization signals responsive to the first clock signal, said synchronization signals simulating a timing of some of the plurality of input data signals;
a second circuit responsive to a second clock signal, said second circuit receiving said plurality of synchronization signals and re-timing said captured data signals to be aligned with said second clock signal based on said synchronization signals.
31. The system device of claim 30, wherein said first circuit is controllable by first and second clock edge selection signals such that some of said plurality of synchronization signals are aligned with a first transition of the first clock signal and the remaining of said plurality of synchronization signals are aligned with a second transition of the first clock signal.
32. The system of claim 30, wherein said data capture circuit comprises:
a plurality of first latch circuits, each first latch circuit having a first input for receiving the first clock signal and a second input for receiving respective input data signals, each first latch circuit being controllable to latch its respective input data signals such that the latched input data signals have a data envelope corresponding to N number of cycles of the first clock signal, where N>1.
33. The system of claim 32, wherein N is three.
34. The system of claim 30, wherein said second circuit comprises:
a reset circuit for generating a synchronization request signal, said reset circuit coupled to said synchronization signals and the second clock signal, said reset circuit outputting said synchronization request signal based on a timing of said synchronization signals with respect to the second clock signal;
a selection circuit for generating at least one selection signal responsive to said synchronization request signal; and
a data generator receiving said at least one selection signal and said captured input signals and re-timing said captured input data signals to be aligned with said second clock signal responsive to said at least one selection signal.
35. A method of operating a memory device, said method comprising the steps of:
receiving a plurality of first input signals responsive to a first clock signal;
latching the received first input signals such that each latched input signal has a data envelope corresponding to N number of cycles of the first clock signal, where N>1; and
outputting re-timed first input signals in accordance with transitions of a second clock signal, wherein the data envelope of each latched first input signal ensures that the latched first input signals are valid when re-timed.
36. The method of claim 35, wherein said latching step comprises:
latching a first portion of the first input signals to a first edge of the first clock signal; and
latching a second portion of the first input signals to a second edge of the first clock signal.
37. The method of claim 36, wherein said re-timing step comprises:
receiving said latched first and second portions; and
combining said first and second portions in accordance with transitions of the second clock signal.
38. The method of claim 35, further comprising the steps of:
receiving a second input signal; and
latching the second input signal such that the second input signal has a data envelope corresponding to N number of cycles of the first clock signal, where N>1, wherein said re-timing step receives the latched second input and uses it re-time the first input signals.
39. The method of claim 35 further comprising the steps of:
generating synchronization signals simulating a timing of the first input signals; and
synchronizing circuitry responsible for capturing the first input signals to circuitry responsible for outputting the re-timed first input signals.
40. The method of claim 39, wherein said synchronizing step comprises:
generating a synchronization request signal based on said synchronization signals;
generating at least one selection signal responsive to said synchronization request signal; and
generating the re-timed first input signals responsive to the at least one selection signal.
41. The method of claim 35, wherein N is three.
42. The method of claim 35, wherein all of the latched first input signals remains valid for a period sufficiently long enough so that said re-timing step circuit can output the re-timed first input signals regardless of voltage variations effecting a timing of the memory device.
43. The method of claim 35, wherein all of the latched first input signals remains valid for a period sufficiently long enough so that said re-timing step circuit can output the re-timed first input signals regardless of temperature variations effecting a timing of the memory device.