1. A circuit comprising:
a first transistor having first and second conduction nodes, a control node configured to receive a first timing signal for causing the first transistor to transition between conducting and non-conducting states, and a bulk node;
a biasing circuit coupled to said bulk node of said first transistor; and
a control circuit configured to
receive at least one feedback signal during application of at least one initial control voltage to said bulk node, and
control said biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the transition, the controlling being based on the at least one feedback signal.
2. The circuit of claim 1, wherein the first transistor includes a back control node and has an semiconductor on insulator (SOI) structure; and wherein said bulk node is coupled to a said back control node of said first transistor.
3. The circuit of claim 2, wherein said first transistor comprises a layer of insulator, and a semiconductor layer isolated from said back control node by said a layer of insulator.
4. The circuit of claim 1, further comprising a capacitor coupled to said second conduction node; and wherein the first conduction node is configured to define an input node of a track and hold circuit.
5. The circuit of claim 1, further comprising a second transistor having first and second conduction nodes, a control node configured to receive a second timing signal for causing the second transistor to transition between conducting and non-conducting states, and a bulk node; wherein the first and second timing signals comprise differential signals; wherein said biasing circuit is coupled to said bulk further node of said second transistor; and wherein said control circuit is further configured to control said biasing circuit to apply a second control voltage to said bulk further node of said second transistor to adjust the timing of the transition of the second transistor.
6. The circuit of claim 5, further comprising a current source; wherein the first conduction nodes of said first and second transistors are coupled to said a current source; further comprising a third transistor having
a first conduction node coupled to a said second conduction node of the first transistor, and
a control node coupled to the second conduction of the second transistor, the control node of said third transistor further receiving an input signal to be sampled.
7. The circuit of claim 5, further comprising:
a fourth transistor having a first conduction node coupled to a first voltage signal, a control node coupled to a second voltage signal, and a second conduction node coupled to an output node; and
a fifth transistor having a first conduction node coupled to a third voltage signal, a control node coupled to a fourth voltage signal, and a second conduction node coupled to said output node,
said first and second transistors configured to generate said first and second voltage signals, said first and second voltage signals being both referenced to a first supply voltage, said third and fourth voltage signals being both referenced to a second supply voltage.
8. The circuit of claim 7, wherein said first and second transistors are configured to:
generate said first voltage signal by offsetting said first supply voltage by an amount based upon the first and second timing signals; and
generate said second voltage signal by offsetting said first supply voltage by an amount based upon said first and second timing signals.
9. The circuit of claim 8, further comprising:
a first branch configured to said first voltage signal and comprising a resistor coupled to said first supply voltage and in series with said first transistor; and
a second branch configured to generate said second voltage signal and comprising a resistor coupled to said first supply voltage and in series with said second transistor.
10. The circuit of claim 7, wherein each of said first and second timing signals has a voltage swing of less than 0.6 V.
11. The circuit of claim 7, wherein each of said first and second timing signals each has a first voltage swing; and wherein an output signal generated at said output node has a second voltage swing greater than said first voltage swing.
12. The circuit of claim 1, wherein the control circuit is configured to control said biasing circuit to generate the first control voltage to have a constant level to adjust the timing of the transition by a first amount.
13. The circuit of claim 12, wherein said control circuit is configured to control, based on at least one feedback signal received by the control circuit during application of at least one initial control voltage to said bulk node; and wherein the biasing circuit is configured to generate said constant level of the first control voltage.
14. A method of modifying timing of at least one of a plurality of transitions between conducting and non-conducting states of a first transistor having first and second conduction nodes, a control node, and a bulk node, the method comprising:
applying to the control node of said first transistor a first timing signal for causing the first transistor to transition between the conducting and non-conducting states; and
controlling, by a control circuit, a biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the at least one of said plurality of transitions of the first transistor, the controlling being based upon at least one feedback signal received by the control circuit during application of at least one initial control voltage to said bulk node.
15. The method of claim 14, wherein controlling the biasing circuit to apply the first control voltage comprises controlling the biasing circuit to generate the first control voltage to have a constant level to adjust the timing of the at least one of said plurality of transitions by a first amount.
16. The method of claim 15, wherein the biasing circuit is configured to generate said constant level of the first control voltage.
17. A circuit comprising:
a first transistor having first and second conduction nodes, a control node configured to receive a first timing signal for causing the first transistor to transition between conducting and non-conducting states, and a bulk node;
a biasing circuit coupled to the bulk node of said first transistor;
a second transistor having first and second conduction nodes, a control node configured to receive a second timing signal for causing the second transistor to transition between conducting and non-conducting states, and a bulk node coupled to said biasing circuit, the first and second timing signals comprising differential signals; and
a control circuit configured to
receive at least one feedback signal during application of at least one initial control voltage to said bulk node,
control said biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the transition, the controlling being based on the at least one feedback signal, and
control said biasing circuit to apply a second control voltage to said bulk node of said second transistor to adjust the timing of the transition of the second transistor.
18. A circuit comprising:
a first transistor having first and second conduction nodes, a control node configured to receive a first timing signal for causing the first transistor to transition between conducting and non-conducting states, and a bulk node;
a biasing circuit coupled to said bulk node of said first transistor; and
a control circuit configured to
receive at least one feedback signal during application of at least one initial control voltage to said bulk node,
control said biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the transition, the controlling being based on the at least one feedback signal, and
control said biasing circuit to generate the first control voltage to have a constant level to adjust the timing of the transition by a first amount.
19. A method of modifying timing of at least one of a plurality of transitions between conducting and non-conducting states of a first transistor having first and second conduction nodes, a control node, and a bulk node, the method comprising:
applying to the control node of said first transistor a first timing signal for causing the first transistor to transition between the conducting and non-conducting states; and
controlling, by a control circuit, a biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the at least one of said plurality of transitions of the first transistor, the controlling being based upon at least one feedback signal received by the control circuit during application of at least one initial control voltage to said bulk node, the controlling comprising operating the biasing circuit to generate the first control voltage to have a constant level to adjust the timing of the at least one of said plurality of transitions by a first amount.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus for identifying a work in a digital processing system comprising:
means for selecting a portion of data of an unknown work;
means for detecting each event in said portion of data of said unknown work;
means for determining a metric between each successive event in said portion of data in said unknown work;
means for generating a list of metrics between said events for said unknown work;
means for comparing said list of metrics for said unknown works to a list of metrics for a known work; and
means for determining said unknown work is a copy of said known work responsive to a match between said list of metrics of said unknown work and said list of metrics for said known work.
2. The apparatus of claim 1 further comprising:
means for comparing said list of metrics of said unknown work to a plurality of lists of metrics wherein each list of metrics is for a known work responsive to a determination that said list of metrics of said unknown work did not match said list of metrics of said known work;
means for determining said unknown work is a copy of one of said known works responsive to a match of said list of metrics of said unknown work and said one of said plurality of lists that represents said one of said known works.
3. The apparatus of claim 2 further comprising:
means for generating a group of said plurality of lists of metrics from known works that are likely to match said unknown work.
4. The apparatus of claim 1 further comprising:
means for receiving a segment of data of said unknown work; and
means for selecting said portion of data from said segment of data received.
5. The apparatus of claim 1 wherein said means for receiving said segment of data comprises:
means for reading said data from memory.
6. The apparatus of claim 1 wherein said step of receiving said segment of data comprises:
means for receiving packets over a network wherein each packet includes a portion of said data;
means for extracting said data from said packets; and
means for reassembling said segment of data from said packets.
7. The apparatus of claim 1 wherein said means for receiving said segment of data comprises:
means for reading said segment from a media storing said segment of data.
8. The apparatus of claim 1 further comprising:
means for determining whether said unknown work is an authorized copy of said known work responsive to a determination that said unknown work is a copy of said known work.
9. The apparatus of claim 8 further comprising:
reporting said unknown work is an unauthorized copy responsive to a determination that said unknown work is an unauthorized copy of said known work.
10. The apparatus of claim 8 further comprising:
means for performing a business rule in response to a determination that said unknown work is an unauthorized copy.
11. The apparatus of claim 1 further comprising:
means for performing a secondary test responsive to a determination that said list of said unknown work does match said list of said known work.
12. The apparatus of claim 1 further comprising;
means for performing a secondary test responsive to a determination that said comparison between said list of said unknown work and said list of said known work are inconclusive.
13. The apparatus of claim 1 further comprising:
means for performing a secondary test to verify an identity of said unknown work responsive to a determination that said list of said unknown work matches said known work.
14. The apparatus of claim 1 wherein said means for comparing comprises:
means for receiving said list of metrics of said unknown work and said list of metrics of said known work;
means for determining a number of events in said list of metrics for said unknown work that match events in said list of metric for said known work;
means for determining whether said number at least equals a threshold; and
means for returning a match responsive to said number being at least equal to said threshold.
15. The apparatus of claim 14 wherein said means for determining said number comprises:
means for aligning an Mth element of said list of metrics of said unknown work with an Nth element of said list of metrics for said known work;
means for performing a first comparison of said lists starting from said Mth element in said list of metrics for said unknown list and said Nth element in said list of metrics for said known work;
means for determining whether said lists match from said Mth element and said Nth element match; and
means for determining a match responsive to a determination said lists match.
16. The apparatus of claim 14 further comprising:
means for recursively determining whether elements of said list of metrics for said unknown work match elements of said list of metrics for said known work.
17. The apparatus of claim 14 wherein said means for determining a match between said list of metrics for said unknown work and said list of metrics for said known work further comprises:
means for determining a match when a number of hits surpasses a threshold.
18. The apparatus of claim 14 wherein said means for determining a match between said list of metrics for said unknown work and said list of metrics for said known work further comprises:
means for determining there is no match responsive to a number of misses being greater than a second threshold.
19. The apparatus of claim 14 wherein said means for determining a match between said list of metrics for said unknown work and said list of metrics for said known work further comprises:
means for receiving said list of metrics for said unknown work starting at the Mth element;
means for receiving said list of metrics of said known work starting at the Nth element;
means for generating a list of associated pairs wherein each M+X element of said list of metrics for said unknown work is paired with the N+X element of said list of metrics for said known work; and
means for computing a regression line through said associated pair in said list of associated pairs.
20. The apparatus of claim 19 wherein said means for determining a match between said list of metrics for said unknown work and said list of metrics for said known work further comprises:
means for computing an error tolerance from said regression line.
21. The apparatus of claim 19 wherein said means for determining a match between said list of metrics for said unknown work and said list of metrics for said known work further comprises:
means for determining a regression error from said computation of said regression line;
means for comparing said regression error to a regression error threshold; and
means for determining a match between said lists responsive to said regression error being less than said regression error threshold.
22. The apparatus of claim 15 wherein said means for determining a match between said list of metrics for said unknown work and said list of metrics for said known work further comprises:
means for determining a weighted error from said computation of said regression line;
means for comparing said weighted error to a weighted error threshold; and
means for determining a match between said lists responsive to said weighted error being less than said weighted error threshold.
23. The apparatus of claim 15 wherein said means for determining a match between said list of metrics for said unknown work and said list of metrics for said known work further comprises:
means for determining a miss ratio from said computation of said regression line;
means for comparing said miss ratio to a miss ratio threshold; and
means for determining a match between said lists responsive to said miss ratio being less than said miss ratio threshold.
24. The apparatus of claim 15 wherein said means for determining a match between said list of metrics for said unknown work and said list of metrics for said known work further comprises:
means for determining a weighted miss ratio from said computation of said regression line;
means for comparing said weighted miss ratio to a weighted miss ratio threshold; and
means for determining a match between said lists responsive to said weighted miss ratio being less than said weighted miss ratio threshold.