1. A method for reducing power consumption of an Ethernet switching apparatus including a plurality of connection ports, each connected to an Ethernet apparatus, comprising:
checking a state of packet data input through each of the connection ports;
detecting a connection port which has a packet rate lower than a predetermined reference value based on results of the checking;
determining a duration of a PAUSE frame, wherein the determining of the duration comprises setting the duration to a predetermined maximum duration if the amount of packet data input through the detected connection port is smaller than a predetermined threshold reference value and otherwise setting to half of the predetermined maximum duration;
generating a data transfer control frame with respect to the detected connection port and transmitting the generated data transfer control frame to an Ethernet apparatus connected to the detected connection port wherein the data transfer control frame is the PAUSE frame, wherein the transmitting of the data transfer control frame comprises generating the PAUSE frame such that a pause state is maintained for the determined duration.
2. The method of claim 1, wherein the determining of the duration further comprises determining the duration using a grading scheme according to the amount of packet data input through the detected connection port.
3. The method of claim 1, wherein the checking of the state of packet data comprises counting up or down according to the number of packet data input or output through each of the plurality of connection ports and the detecting of the connection port comprises detecting the connection port which has the lowest packet rate among the plurality of connection ports based on the count value.
4. The method of claim 1, wherein the detecting of the connection port comprises detecting the connection port having a low packet rate when underflow occurs in an input buffer in which the input packet data is stored.
5. An Ethernet switching apparatus comprising:
a plurality of connection ports, each connected to an Ethernet apparatus; and
a control unit comprising:
(i) a control frame generating unit to generate a data transfer control frame with respect to a connection port having a packet rate lower than a predetermined reference value among the plurality of connection ports based on a state of packet data input through each connection port and to transmit the generated data transfer control frame to an Ethernet apparatus connected to the connection port having the packet rate lower than the predetermined reference value, wherein the data transfer control frame is a PAUSE frame, and
(ii) a duration setting unit to determine a duration of the PAUSE frame, wherein to determine the duration comprises setting the duration to a predetermined maximum duration if the amount of packet data input through the connection port having the packet rate lower than the predetermined reference value is smaller than a predetermined threshold reference value and otherwise setting to half of the predetermined maximum duration,
wherein the control frame generating unit generates the PAUSE frame such that a pause state is maintained for the determined duration.
6. The Ethernet switching apparatus of claim 5, wherein the duration setting unit further determines the duration using a grading scheme according to the amount of packet data to be transmitted through the connection port having the packet rate lower than the predetermined reference value.
7. The Ethernet switching apparatus of claim 5, further comprising:
one or more packet counters, each to count input and output states of packet data received through a corresponding connection port, wherein the control unit monitors the amount of packet data input through each connection port based on a count value of the counter and identifies a state of packet data.
8. The Ethernet switching apparatus of claim 7, wherein the packet counters are provided to correspond to respective ones of the connection ports.
9. The Ethernet switching apparatus of claim 5, wherein the control unit generates the data transfer control frame when underflow occurs in an input buffer in which the input packet data is stored.
10. The Ethernet switching apparatus of claim 5, wherein the control unit includes a media access controller (MAC).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A long wavelength vertical cavity surface emitting laser configuration comprising:
a semiconductor substrate;
a photodetector located on said semiconductor;
a lower distributed Bragg reflector, which includes multiple layers and is grown on the photodetector;
an active region, which includes multiple semiconductor material layers which emit long wavelength light upon excitation and is grown on the lower distributed Bragg reflector; and
an upper distributed Bragg reflector, which includes multiple layers and is grown on the active region,
wherein the photodetector detects a laser beam emitted from the active region that heads toward semiconductor substrate,
wherein both shoulders of the photodetector are exposed so that a stack including the lower distributed Bragg reflector, the active region, and the upper distributed Bragg reflector has a column shape on the photodetector, and
wherein the photodetector comprises a PIN photodiode having a p-doped layer, an n-doped layer and an absorbing layer, and further comprising at least one upper photodiode formed on the upper distributed Bragg reflector, at least an intermediate electrode formed on the PIN electrode, and a lower electrode formed on a bottom surface of the semiconductor substrate, said lower electrode being shared by the active region and the PIN photodiode.
2. The long wavelength vertical cavity surface emitting laser configuration of claim 1, wherein the substrate is made of gallium arsenide (GaAs).
3. The long wavelength vertical cavity surface emitting laser configuration of claim 1, wherein the substrate is made of indium phosphide (InP).
4. The long wavelength vertical cavity surface emitting laser configuration of claim 1, wherein the substrate is made of one of GaAs and InP.
5. The long wavelength vertical cavity surface emitting laser configuration of claim 1, wherein the substrate is made of GaAs, and the active region is made of an InGaAs quantum well layer.
6. The long wavelength vertical cavity surface emitting laser of claim 1, wherein the substrate is made of GaAs, and the active region is made of one of an indium gallium arsenide nitride (InGaAsN) quantum well layer, and an In(Ga)(N)As quantum dot layer.
7. The long wavelength vertical cavity surface emitting laser of claim 1, wherein the substrate is made of GaAs, and an absorbing layer of the photo detector includes one of an InGaAs quantum well, an indium gallium arsenide nitride (InGaAsN) quantum well, and an In(Ga)(N)As quantum dot.
8. The long wavelength vertical cavity surface emitting laser configuration of claim 1, wherein each of the upper and lower distributed Bragg reflectors is an (Al)GaAsAl(Ga)As stack.
9. The long wavelength vertical cavity surface emitting laser configuration of claim 4, wherein each of the upper and lower distributed Bragg reflectors is an (Al)GaAsAl(Ga)As stack.
10. The long wavelength vertical cavity surface emitting laser configuration of claim 1, wherein the substrate is made of InP, and the active region is made of an InGaAsP quantum well layer.
11. The long wavelength vertical cavity surface emitting laser configuration of claim 1, wherein the substrate is made of InP, and the active region is made of one of an InGaAlAs quantum well layer, an InGaAs quantum well layer, an In(Ga)(N)As quantum dot layer, and an aluminum gallium arsenide stibium (AlGaAsSb) quantum well layer.
12. The long wavelength vertical cavity surface emitting laser configuration of claim 1, wherein the substrate is made of InP, and an absorbing layer of the photo detector includes one of an InGaAsP quantum well, an InGaAlAs quantum well, an InGaAs quantum well, an In(Ga)(N)As quantum dot, and an AlGaAsSb quantum well.
13. The long wavelength vertical cavity surface emitting laser configuration of claim 10, wherein each of the upper and lower distributed Bragg reflectors is an InPInGaAsP or InPInGaAlAs stack.
14. The long wavelength vertical cavity surface emitting laser configuration of claim 11, wherein each of the upper and lower distributed Bragg reflectors is an InPInGaAsP or InPInGaAlAs stack.
15. The long wavelength vertical cavity surface emitting laser configuration of claim 1, wherein the absorbing layer has a band gap that is less than or the same as that of the active layer.